Blockwise parallel frozen bit generation for polar codes

ABSTRACT

An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator ( 3403 ) configured to successively perform a bit pattern generation process over a series (t=┌n/w▴) of clock cycles; and a counter (c,  4203 ), operably coupled to the bit pattern generator ( 3403 ) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w▴) of clock cycles. The bit pattern generator ( 3403 ) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (b k,n ) in each successive t=┌n/w▴ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.

FIELD OF THE INVENTION

The field of the invention relates to an electronic device configured toperform polar coding and a method for bit pattern generation. Theinvention is applicable to, but not limited to, a bit pattern generationfor a polar encoder and a polar decoder for current and futuregenerations of communication standards.

BACKGROUND OF THE INVENTION

In accordance with the principles of Forward Error Correction (FEC) andchannel coding, polar coding [1] may be used to protect informationagainst the effects of transmission errors within an imperfectcommunication channel, which may suffer from noise and other detrimentaleffects. More specifically, a polar encoder is used in the transmitterto encode the information and a corresponding polar decoder is used inthe receiver to mitigate transmission errors and recover the transmittedinformation. The polar encoder converts an information block comprisingK bits into an encoded block comprising a greater number of bits M>K,according to a prescribed encoding process. In this way, the encodedblock conveys the K bits of information from the information block,together with M-K bits of redundancy. This redundancy may be exploitedin the polar decoder according to a prescribed decoding process, inorder to estimate the values of the original K bits from the informationblock. Provided that the condition of the communication channel is nottoo severe, the polar decoder can correctly estimate the values of the Kbits from the information block with a high probability.

The polar encoding process comprises three steps. In a first informationblock conditioning step, redundant bits are inserted into theinformation block in prescribed positions, in order to increase its sizefrom K bits to N bits, where N is a power of two. In a second polarencoding kernal step, the N bits of the resultant kernal informationblock are combined in different combinations using successive eXclusiveOR (XOR) operations, according to a prescribed graph structure. Thisgraph structure comprises n=log₂(N) successive stages, each comprisingN/2 XOR operations, which combine particular pairs of bits. In a thirdstep, encoded block conditioning is applied to the resultant kernalencoded block, in order to adjust its size from N bits to M bits. Thismay be achieved by repeating or removing particular bits in the kernalencoded block according to a prescribed method, in order to produce theencoded block, which is transmitted over a channel or stored in astorage media.

A soft encoded block is received from the channel or retrieved from thestorage media. The polar decoding process comprises three steps, whichcorrespond to the three steps in the polar encoding process, but in areverse order. In a first encoded block conditioning step, redundantsoft bits are inserted or combined into the soft encoded block inprescribed positions, in order to adjust its size from M soft bits to Nsoft bits, where N is a power of two. In a second polar decoding kernalstep, the N soft bits of the resultant kernal encoded block are combinedin different combinations using a Successive Cancellation (SC) [1] orSuccessive Cancellation List (SCL) [7] process, which operates on thebasis of the prescribed graph structure. In a third step, informationblock conditioning is applied to the resultant recovered kernalinformation block, in order to reduce its size from N bits to K bits.This may be achieved by removing particular bits in the recovered kernalinformation block according to a prescribed method, in order to producethe recovered information block.

In a context of a polar encoder, the information block conditioningcomponent 101 interlaces the K information bits with N-K redundant bits,which may be frozen bits [1], Cyclical Redundancy Check (CRC) bits [2],Parity Check (PC)-frozen bits [3], User Equipment Identification (UE-ID)bits [4], or hash bits [5], for example. Here, frozen bits may alwaysadopt a logic value of ‘0’, while CRC or PC-frozen bits or hash bits mayadopt values that are obtained as functions of the information bits, orof redundant bits that have already been interlaced earlier in theprocess. The information block conditioning component 101 generatesredundant bits and interlaces them into positions that are identified bya prescribed method, which is also known to the polar decoder. Theinformation block conditioning component 101 may also include aninterleaving operation, which may implement a bit-reversal permutation[1] for example.

In a context of a polar encoder, the encoded block conditioningcomponent 103 may use various techniques to generate the ‘M’ encodedbits in the encoded block 107, where ‘M’ may be higher or lower than‘N’. More specifically, repetition [6] may be used to repeat some of the‘N’ bits in the kernel encoded block, while shortening or puncturingtechniques [6] may be used to remove some of the ‘N’ bits in the kernelencoded block. Note that shortening removes bits that are guaranteed tohave logic values of ‘0’, while puncturing removes bits that may haveeither of logic ‘0’ or ‘1’ values. The encoded block conditioningcomponent may also include an interleaving operation.

The input to the encoded block conditioning component 110 of the polardecoder is a soft encoded block. In order to convert the M encoded LLRsinto ‘N’ kernal encoded LLRs, infinite-valued LLRs may be interlacedwith the soft encoded block 109, to occupy the positions within the softkernal encoded block that correspond to the ‘0’-valued kernal encodedbits that were removed by shortening in the polar encoder. Likewise,‘0’-valued LLRs may be interlaced with the soft encoded block 109, tooccupy the positions where kernal encoded bits were removed bypuncturing. In the case of repetition, the LLRs that correspond toreplicas of a particular kernal encoded bit may be summed and placed inthe corresponding position within the soft kernal encoded block 109. Acorresponding deinterleaving operation may also be performed, ifinterleaving was employed within the encoded block conditioningcomponent 103 of the polar encoder.

The input to the information block conditioning component 112 of thepolar decoder is a recovered kernal information block 114. The recoveredinformation block may be obtained by removing all redundant bits fromthe recovered kernal information block 114. A correspondingdeinterleaving operation may also be performed, if interleaving wasemployed within the information block conditioning component 101 of thepolar encoder.

During the implementation of the four block conditioning components, itis challenging to achieve the flexibility that is required to enablebits or soft bits (which may be represented in the form of LLRs) to beinserted into or removed from arbitrary positions within thecorresponding blocks, where these positions vary depending on theparticular combination of K, N and M. This is particularly challengingin the implementation of flexible polar encoders and decoders, whichallow K, N and M to vary from block to block, during run-time. It isparticularly challenging to implement these flexible block conditioningcomponents with a low hardware usage and the ability to complete theblock conditioning processes within a low number of clock cycles. Owingto this challenge, all previous implementations [14, 15] of the blockconditioning components have only processed one bit or soft bit perclock cycle, requiring a total of N clock cycles to complete theprocess.

SUMMARY OF THE INVENTION

The present invention provides an electronic device configured toperform polar coding using block conditioning circuits, an integratedcircuit and a method for block conditioning, as described in theaccompanying claims.

Specific embodiments of the invention are set forth in the dependentclaims.

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details, aspects and embodiments of the invention will bedescribed, by way of example only, with reference to the drawings. Inthe drawings, like reference numbers are used to identify like orfunctionally similar elements. Elements in the FIG's are illustrated forsimplicity and clarity and have not necessarily been drawn to scale.

FIG. 1 illustrates an example top-level schematic of a communicationunit having a polar encoder and polar decoder, adapted according toexample embodiments of the invention.

FIG. 2 illustrates an example graphical representation of the generatormatrices F, F^(⊗2) and F^(⊗3), according to example embodiments of theinvention.

FIG. 3 illustrates an example polar encoding process, using thegraphical representation of the generator matrix F^(⊗3), illustratingthe case where a particular frozen bit pattern is used to convert theK=4 information bits a=[1001] into the M=8 encoded bits b=[00001111],according to example embodiments of the invention.

FIG. 4 illustrates an example block diagram of an interlacerarchitecture, according to some example embodiments of the invention.

FIG. 5 illustrates a more detailed example of an interlacer architecturefor the case of w=4, according to some example embodiments of theinvention.

FIG. 6 illustrates an example table to operate an interlacer, where:w=4, for the case where the k=9 input elements [9, 8, 7, 6, 5, 4, 3, 2,1] are interlaced from right-to-left with 0-valued interlacing elements,according to the n=16-bit pattern [1100011010110101], according to someexample embodiments of the invention.

FIG. 7 illustrates a naive bit pattern generator, for the case wherew=4, according to some example embodiments of the invention.

FIG. 8 illustrates an example table of contents of a bit pattern ROM,when using a Polarization Weight (PW) bit pattern construction of [8]for all combinations of n′{2, 4, 8, 16} and k′{1, 2, 3, . . . , n−1},according to some example embodiments of the invention.

FIG. 9 illustrates an example contents of the rank ROM 3801, when usingthe PW bit pattern construction of [8] for all n′{2, 4, 8, 16, 32},according to some example embodiments of the invention.

FIG. 10 illustrates a bit pattern generator exploiting the nestedproperty, for the case where w=4, according to some example embodimentsof the invention.

FIG. 11 illustrates a bit pattern generator exploiting the nested andsymmetric properties, for the case where w=4, according to some exampleembodiments of the invention.

FIG. 12 illustrates a bit pattern generator exploiting the nested,recursive and arithmetic properties, for the case where w=4, accordingto some example embodiments of the invention.

FIG. 13 illustrates circuits for generating w bits from a particular bitpattern in each step of the encoded block conditioning process: (a)Block puncturing; (b) Block shortening; (c) Bit reversal puncturing; and(d) Bit reversal shortening, according to some example embodiments ofthe invention.

FIG. 14 illustrates a high-level flowchart of a polar coder operationsperformed by a bit pattern generator in accordance with some exampleembodiments of the invention.

FIG. 15 illustrates a typical computing system that may be employed inan electronic device or a wireless communication unit to perform polarencoding operations in accordance with some example embodiments of theinvention.

FIG. 16 provides a schematic of the proposed hardware implementationsfor frozen bit insertion and removal, in accordance with some exampleembodiments of the invention.

FIG. 17 exemplifies elements Q_(N) ^(←)[c,i] of the reversed sequenceROM for N=64 and w_(Q)=8, where i∈[0, w_(Q)−1] and c∈[0, N/w_(Q)−1], inaccordance with some example embodiments of the invention.

FIG. 18 exemplifies elements Q_(N) ^(π)[c, i] of the interleavedsequence ROM for N=64 and w_(Q)=8, where i∈[0, w_(Q)−1] and c∈[0,N/w_(Q)−1], in accordance with some example embodiments of theinvention.

FIG. 19 exemplifies elements π_(N) ⁻¹ [c,i] of the deinterleaver ROM forN=64 and w_(R)=4, where i∈[0, w_(R)−1] and c∈[0, N/w_(R)−1], inaccordance with some example embodiments of the invention.

FIG. 20 exemplifies elements R_(N)[c,i] of the rank ROM for N=64 andw_(R)=4, where i∈[0, w_(R)−1] and c∈[0, N/w_(R)−1], in accordance withsome example embodiments of the invention.

FIG. 21 provides a flow chart of the proposed hardware implementationsfor frozen bit insertion and removal, in accordance with some exampleembodiments of the invention.

FIG. 22 exemplifies elements of the bit pattern generated in each of theN/w_(R)=16 clock cycles of the second sub-process (identified as 4702)for K=32, M=68, N=64 and w_(R)=4, in accordance with some exampleembodiments of the invention. In this case, repetition is used and k=32.Since M<N is not satisfied, no clock cycles are used to complete thefirst sub-process (identified as 4701), irrespective of w_(Q).

FIG. 23 exemplifies elements of the bit pattern generated in each of theN/w_(R)=16 clock cycles of the second sub-process for K=32, M=56, N=64and w_(R)=4, in accordance with some example embodiments of theinvention. In this case, shortening is used and k=40. When w_(Q)=8, fiveclock cycles are used to complete the first sub-process 4701.

FIG. 24 exemplifies elements of the bit pattern generated in each of theN/w_(R)=16 clock cycles of the second sub-process for K=24, M=56, N=64and w_(R)=4, in accordance with some example embodiments of theinvention. In this case, puncturing is used and k=25. When w_(Q)=8, fourclock cycles are used to complete the first sub-process 4701.

FIG. 25 plots an example of a number of clock cycles required by thefirst sub-process 4701 as a function of M∈[17,1024] and K∈[[M/8], M−1],for the worst case where w_(Q)=1, in accordance with some exampleembodiments of the invention. When w_(Q) adopts the value of a higherpower of two, these numbers of clock cycles may be linearly scaled downand then rounded up to the nearest integer.

FIG. 26 plots an example of a number of clock cycles required by thesecond sub-process as a function of M∈[17,1024] and K∈[[M/8], M−1], forthe worst case where w_(R)=1, in accordance with some exampleembodiments of the invention. When w_(R) adopts the value of a higherpower of two, these numbers of clock cycles may be linearly scaled downand then rounded up to the nearest integer.

DETAILED DESCRIPTION

Several sequences have been proposed for the selection of informationbits during information block conditioning within a polar encoder[8-12]. These sequences may be used to obtain a bit pattern vectorb_(k,n), in which k out of n bits have the value ‘1’, where n is a powerof two greater than k. These 1-valued bits identify the positions wherethe k information bits should be inserted into the n-bit kernalinformation block. The process of generating the bit pattern may becompleted over a series of t=┌n/w┐ clock cycles at the start of thepolar encoding process, where a sub-process of the bit patterngeneration process is completed in each successive clock cycle. Here,successive sub-sets of w bits from the bit pattern vector b_(k,n) may beused to control the insertion of information bits into successivesub-sets of w bits for the kernal information block. Throughout thisprocess, these successive w-bit sub-sets of the kernal information blockmay be simultaneously funnelled into a polar encoder kernal having acorresponding input width of w, such as the design of [13], which hasdemonstrated w=32. In this way, the insertion of the k information bitsinto the n-bit kernal information block may impose no additional latencyupon the polar encoding process. Likewise, similar benefits can beobtained in the polar decoder, when extracting the k recoveredinformation bits from the recovered kernal information block. Note thatthe proposed approach processes w pattern bits in each step, which is incontrast to the block conditioning modules of previous efforts [14, 15],which are only capable of processing a single pattern bit in each step.

In a first aspect, examples of the present invention an electronicdevice configured to perform polar coding is described. The electronicdevice includes a bit pattern generator configured to successivelyperform a bit pattern generation process over a series (t=┌n/w┐) ofclock cycles; and a counter, operably coupled to the bit patterngenerator and configured to count a number of successive bit patterngeneration sub-processes over the series (t=┌n/w┐) of clock cycles. Thebit pattern generator is configured to: provide a successive sub-set of(w) bits from a bit pattern vector (b_(k,n)) in each successive t=┌n/w┐clock cycle; where the bit pattern vector comprises n bits, of which ‘k’bits adopt a first binary value and n−k bits adopt a complementarybinary value.

In this manner, parallel processing may be used to reduce the number ofclock cycles required to complete the bit pattern generation process.

In some examples, the bit pattern generator circuit may include a bankof (w) comparators, and wherein each of w bit pattern bits {b₀, b₁, b₂,. . . , b_(w−1)} may be obtained from a corresponding comparator in thebank of w comparators. In this manner, w bit patterns bits may begenerated in each clock cycle, using only low complexity hardware.

In some examples, the bit pattern generator is configured to perform thebit pattern generation process as a part of at least one of: aninformation block conditioning circuit in an encoder that receives aninformation block as the input data block and outputs an n-bit kernalinformation block; an encoded block conditioning circuit in an encoderthat receives an n-bit kernal encoded block as the input data block andoutputs an encoded block; an encoded block conditioning circuit in adecoder that receives a soft encoded block as the input data block andoutputs an n-soft-bit soft kernal encoded block; an information blockconditioning circuit in a decoder that receives an n-bit recoveredkernal information block as the input data block and outputs a recoveredinformation block. In some examples, the bit pattern generator may beconfigured to perform in at least one of: an interlacer wherebysuccessive w-bit sub-sets of the kernel information block are funnelledinto a polar encoder kernal) having a corresponding input width of ‘w’bits; and an interlacer whereby successive w-soft-bit sub-sets of thesoft kernal encoded block are funnelled into a polar decoder kernalhaving a corresponding input width of ‘w’ soft bits. In this manner,parallel processing may be used to reduce the number of clock cyclesrequired to complete the block conditioning and interlacing processes.

In some examples, the bit pattern generator may be configured to obtainthe bit pattern vector (b_(k,n)) in which ‘k’ out of ‘n’ bits has thefirst binary value and ‘n−k’ out of ‘n’ bits has the complementarybinary value, where n is a power of two greater than k. In this manner,compatibility is ensured with the polar coding kernal process, whichoperates on blocks having a length which is a power of two.

In some examples, the bit pattern generator circuit may be operablycoupled to a bit pattern Read Only Memory, ROM, and configured to storetherein a set of supported bit pattern vectors (b_(k,n)). In thismanner, any arbitrary set of bit patterns may be supported, even ifthere are no nested relationships between them. In some examples, theset of supported bit pattern vectors, b_(k,n), may be generated in anoff-line pre-computation process and stored in the bit pattern ROM forreading from during an on-line bit pattern generation process. In thismanner, no on-line computation is required, reducing the on-linecomplexity of the bit pattern generator. In some examples, the bitpattern ROM may have a width of ‘w’ bits and each bit pattern vector(b_(k,n)) may be stored across a number ┌n/w┐ of consecutive addresses,wherein for some examples, for n<w, the bit pattern vector (b_(k,n)) maybe appended with a number, w−n, of dummy bits, such that bit patternvector (b_(k,n)) occupies a width of a single address in the bit patternROM. In this manner, ‘w’ bit pattern bits may be read in each clockcycle, reducing the number of clock cycles required to obtain thecomplete bit pattern vector. Furthermore, the special case of very shortbit pattern vectors can be accommodated naturally, without therequirement for a separate solution.

In some examples, the bit pattern ROM may be operably coupled to a firstlook-up table, wherein the values of ‘k’ and ‘n’ are used as an input toas well as to index the first look-up table in order to identify a startaddress of each respective bit pattern vector (b_(k,n)). In this manner,each bit pattern vector can be located within the bit pattern ROMwithout the requirement for any on-line computation, for example. Insome examples, the counter may be operably coupled to the bit patternROM, and configured to increment a counter value from ‘0’ to ‘t−1’wherein the counter value may be used as an offset from a start addressof the bit pattern ROM in order to read successive w-element sub-sets(b₀, b₁, b₂, . . . , b_(w−1)) of the bit pattern vector (b_(k,n)). Inthis manner, the bit pattern vector may be read from the bit pattern ROMusing only low complexity addressing hardware.

In some examples, the bit pattern generator may include a rank ROMconfigured to store information sufficient to obtain a rank vector(R_(n)) for each supported length of the bit pattern, ‘n’. In thismanner, the ROM capacity may be significantly reduced relative tostoring each supported bit pattern vector separately. Furthermore, therank vector R_(n) may be used to generate the bit pattern vector b_(k,n)without the requirement for a complex sort or interleaving operation, asis required when using the index vector Q_(n) as the basis of the bitpattern generation process. In some examples, the rank vector (R_(n))for a particular length of the bit pattern, ‘n’, may include integers ina range of ‘0’ to ‘n−1’, permuted in an order that corresponds to a rankof each bit position. In some examples, a rank may indicate a maximumvalue for the number ‘k’ out of ‘n’ bits in the bit pattern adopting thefirst binary value, for which a corresponding bit in the bit patternvector (b_(k,n)) has the complementary binary value. In this manner, therank vector contains all information necessary to generate all bitpattern vectors having the length of ‘n’ bits, when the bit patternvectors obey the nested property.

In some examples, a length of the bit pattern n may be used to index asecond look-up table, in order to identify the start address of eachparticular rank vector (R_(n)). In this manner, each bit pattern vectorcan be located within the bit pattern ROM without the requirement forany on-line computation, for example. In some examples, the rank ROM mayinclude multiple multiplexed rank ROMs, wherein one multiplexed rank ROMmay be configured to store the rank vector (R_(n)) corresponding to eachsupported value of the length of the bit pattern n. In this manner, eachseparate multiplexed rank ROM may adopt a different bit width for thestored fixed point numbers. Also, the requirement for a look up table tostore the start addresses is eliminated. In some examples, the bitpattern vector (b_(k,n)) may be generated for a respective combinationof the number, k, of bits in the bit pattern adopting the first binaryvalue and the length of the bit pattern ‘n’ using the bank of (w)comparators that may be configured to compare each element of the rankvector (R_(n)) with ‘k’. In some examples, each comparison of theelement of the rank vector (R_(n)) with ‘k’ may be performed todetermine whether the element is less than ‘k’. In this manner, w bitsof the bit pattern vector may be generated in each clock cycle, usingonly low complexity hardware. In some examples, all entries in the rankROM may be stored using fixed point numbers having a width oflog₂(n_(max)) bits, where n_(max) is a maximum of the supported bitpattern lengths. In this manner, a common fixed point number width isused throughout the bit pattern generator, avoiding the requirement toconvert between fixed point number widths. In some examples, all entriesin the rank ROM for particular values of n may be stored using fixedpoint numbers having a width of log₂(n) bits. In some examples, eachaddress of the rank ROM may be configured to store w fixed-pointnumbers. In this manner, the ROM capacity may be reduced relative tousing a constant fixed point number width for all value of n. In someexamples, the rank ROM, in cases where n<w, may be configured to appendthe rank vector (R_(n)) with w-n dummy elements, such that the rankvector (R_(n)) occupies a width of a single address in the rank ROM. Inthis manner, the special case of very short bit pattern vectors can beaccommodated naturally, without the requirement for a separate solution.

In some examples, the rank ROM may be operably coupled to the counter,such that during each successive sub-process of the bit patterngeneration process, the counter may be configured to increment a countervalue from ‘0’ to ‘t−1’ wherein the counter value may be used as anoffset from a start address of the rank ROM in order to read successivew-element sub-sets of the rank vector (R_(n)). In this manner, the bitpattern vector may be read from the bit pattern ROM using only lowcomplexity addressing hardware. In some examples, a bit pattern bit ofthe bit pattern vector b_(k,n) may be obtained by representing both arank value and k using a two's complement fixed-point numberrepresentation, and the bit pattern generator circuit may perform a twoscomplement subtraction of ‘k’ from the rank value and then use a mostsignificant bit, MSB, as a value of the bit pattern bit. In this manner,the bit pattern bit may be obtained using only low complexity hardware.

In some examples, the rank ROM may be configured to store a first halfof each rank vector (R_(n)), when the bit pattern vectors (b_(k,n))follow a symmetric property. In some examples, the symmetric propertymay be satisfied if any pair of elements in the rank vector (R_(n))having the indices i and n−i−1 sum to n−1, for all n and for all i∈[0,n−1]. In some examples, the rank ROM may include a width of ‘w’ ranks,such that only a first half of each rank vector (R_(n)) is stored across┌n/(2w)┐ consecutive addresses, where n is a bit pattern lengthsupported by the rank vector (R_(n)). In this manner, the capacity ofthe rank ROM may be reduced by 50% relative to storing the entirety ofeach rank vector.

In some examples, for n/2<w, the rank vector (R_(n)) may be appendedwith ‘w−n’ dummy elements and stored across a width of a single addressin the rank ROM. In this manner, the special case of very short bitpattern vectors can be accommodated naturally, without the requirementfor a separate solution.

In some examples, during a first half of successive operations of thebit pattern generation process when c<┌n/(2w)┐, successive w-elementsub-sets of the rank vector (R_(n)) may be obtained from incrementaladdresses in the rank ROM 3801, where the offset from the start addressof the rank ROM may be given by c. In this manner, the bit patternvector may be read from the bit pattern ROM using only low complexityaddressing hardware. In some examples, the electronic device may furtherinclude a bank of w multiplexers operably coupled to the rank ROM,wherein during a first half of successive operations of the bit patterngeneration process the bank of w multiplexers may maintain the order ofthe w pattern bits {b₀, b₁, b₂, . . . , b_(w−1)}. In some examples, abit pattern bit of the bit pattern vector b_(k,n) may be obtained byrepresenting both a rank value and k using a two's complementfixed-point number representation, and the bit pattern generator circuitperform a subtraction of ‘k’ from the rank value and then uses a mostsignificant bit, MSB, as a value of the bit pattern bit. In this manner,the bit pattern bit may be obtained using only low complexity hardware.

In some examples, the electronic device may further include amultiplexer operably coupled to the rank ROM, wherein during a secondhalf of successive operations of the bit pattern generation process whenc≥┌n/(2w)┐, successive w-element sub-sets of the rank vector (R_(n)) maybe obtained from decremental addresses in the rank ROM in a reverseorder, where the offset from the start address of the rank ROM may begiven by the multiplexer and may be derived from the counter value ‘c’as (┌n/w┐−c−1). In this manner, the bit pattern vector may be read fromthe bit pattern ROM using only low complexity addressing hardware.

In some examples, the bit pattern vector (b_(k,n)) may be generated fora respective combination of ‘k’ and ‘n’ using the bank of (w)comparators that may be configured to compare each element of the rankvector (R_(n)) with ‘n−k’. In some examples, each comparison of theelement of the rank vector (R_(n)) with ‘n−k’ may be performed todetermine whether the element of the rank vector (R_(n)) is greater thanor equal to ‘n−k’. In some examples, each comparison of the element ofthe rank vector (R_(n)) with ‘n−k’ may be performed to determine whetherthe element of the rank vector (R_(n)) is less than ‘n−k’ and the resultmay be passed through a NOT logic gate. In this manner, the bit patternbit may be obtained using only low complexity hardware. In someexamples, the bit pattern bit may be obtained by representing both arank value and n−k using a two's complement fixed-point numberrepresentation, and the bit pattern generator circuit may perform asubtraction of n−k from the rank value and then passes a mostsignificant bit, MSB, of a result through a NOT gate. In some examples,the electronic device may further include a bank of w multiplexersoperably coupled to the rank ROM, wherein during a second half ofsuccessive operations of the bit pattern generation process the bank ofw multiplexers may reverse the order of the w pattern bits {b₀, b₁, b₂,. . . , b_(w−1)}. In this manner, the bit pattern bits may be generatedin the correct order, using only low complexity hardware.

In some examples, elements of the rank vector (R_(n)), for a particularvalue of the length of the bit pattern ‘n’ may be stored in rank ROM ina native form or subtracted from ‘n−1’ and stored in rank ROM in asubtracted form. In some examples, each comparison to determine if arank of the rank vector (R_(n)) may be less than ‘k’ may be performed byusing a comparator to determine if the rank in subtracted form may begreater than or equal to ‘n−k’ and each comparison to determine if arank of the rank vector (R_(n)) may be greater than or equal to than‘n−k’ may be performed by using a comparator to determine if the rank insubtracted form is less than ‘k’.

In some examples, the bank of w comparators may be used during both afirst half of successive operations of the bit pattern generationprocess and a second half of successive operations of the bit patterngeneration process. In some examples, the bank of w comparators may beimplemented using twos complement subtractions.

In some examples, the electronic device may further include amultiplexer operably coupled to the bank of w comparators and configuredto select between ‘k’ or ‘n−k’ as an input to the bank of w comparators;and a bank of w NOT logic gates operably coupled to an output of thebank of w comparators and configured to invert an output of thecomparators bank of w comparators. In some examples, the electronicdevice may further include a bank of w multiplexers operably coupled tothe rank ROM, wherein during a second half of successive operations ofthe bit pattern generation process the bank of w multiplexers mayreverse the order of the w pattern bits {b₀, b₁, b₂, . . . , b_(w−1)}.In this manner, the same low complexity hardware may be reduced in boththe first and second halves of the bit pattern generation process.

In some examples, the bit pattern generator may be configured to exploita nested, recursive and arithmetic property of the bit patterns vectors.In this manner, the ROM storage required to generate the bit patternvector may be reduced relative to approaches that store the supportedbit pattern vectors or the rank vectors in ROM. In some examples, arecursive circuit may be used to convert a value of n−k into an indexQ_(n)(n−k) of a bit having an (n−k)th highest bit reliability. In thismanner, the index of the bit having the threshold bit reliability may beidentified with a low complexity. In some examples, the recursivecircuit may be further configured to unpack compressed information, inorder to obtain the index Q_(n)(n−k). In this manner, the decompressionprocess may be configured to unpack only the single index Q_(n)(n−k),rather than the entire index vector Q_(n), reducing the associatedcomplexity.

In some examples, the electronic device may further include anarithmetic circuit operably coupled to a recursive circuit andconfigured to use an arithmetic property that may be satisfied if a bitreliability metric can be obtained for each of the u bits in the bitpattern vector based only on its index in the range ‘0’ to ‘n−1’ toconvert the index (Q_(n)(n−k)) of the bit having the (n−k)th rank into abit reliability metric (β(Q_(n)(n−k))). In this manner, the thresholdbit reliability may be obtained with a low complexity. In some examples,in a Polarization Weight, PW, sequence, the recursive property of thebit pattern vector (b_(k,n)) may be used to determine relationshipsbetween bits in the kernal information block. In some examples, the bitpattern generator circuit may determine: (i) in response to therecursive property of the bit pattern vector (b_(k,n)) being a frozenbit, that other selected bits will also be frozen bits; or (ii) inresponse to the recursive property of the bit pattern vector (b_(k,n))being an information bit, that other selected bits will also beinformation bits. In some examples, in response to the bit patterngenerator circuit determining that a relationship between bits in thekernal information block exists, the bit pattern generator circuit maybe configured to disable at least one arithmetic circuit. In thismanner, the arithmetic calculations of bit reliability may be skipped ifthe corresponding bits have already been determined as being frozen orinformation bits, reducing the power consumption of the bit patterngenerator.

In some examples, the electronic device may further include a registeroperably coupled to the arithmetic circuit and configured to store thebit reliability metric (β(Q_(n)(n−k))) that may be used in the processof generating the bit pattern vector b_(k,n). In this manner, thethreshold bit reliability metric may be stored and used throughout thebit pattern generation process, eliminating the requirement torecalculate this threshold in each successive clock cycle.

In some examples, the electronic device may further include a multiplierand a bank of w−1 adders operably coupled to the counter, wherein,during each successive performance of the bit pattern generation processover a series (t=┌n/w┐) of clock cycles, the counter may be configuredto increment a counter value, c, from 0 to t−1 to obtain bit indices{cw, cw+1, cw+2, . . . , cw+w−1} for successive w-element sub-sets (b₀,b₁, b₂, . . . , b_(w−1)) of the bit pattern vector b_(k,n).

In some examples, the electronic device may further include a bank of‘w’ replicas of the arithmetic circuit that may be configured to computea corresponding sequence of bit reliabilities, β[cw], β[cw+1], β[cw+2],. . . , β[cw+w−1]. In some examples, the bank of (w) comparators may beconfigured to compare the computed corresponding bit reliabilities{β[cw], β[cw+1], β[cw+2], . . . , β[cw+w−1]} with the bit reliabilitymetric (β(Q_(n)(n−k))), in order to obtain the corresponding w elementsof the bit pattern vector b_(k,n) by determining whether thecorresponding bit reliabilities {β[cw], β[cw+1], β[cw+2], . . . ,β[cw+w−1]} are greater than or equal to β(Q_(n)(n−k)). In this manner,the bit reliability metrics associated with w bit pattern bits may becompared with the threshold bit reliability metric in each clock cycle,with a low complexity.

In some examples, the electronic device may further include a bank of‘w’ reverse modules operably coupled via the multiplier and the bank ofw−1 adders to the counter, and configured to reverse an order of bits ina log₂(n)-bit binary representation of each bit index, in order toproduce reversed bit indices. In some examples, the electronic devicemay further include a bank of w comparators operably coupled bank of ‘w’reverse modules and configured to compare either the bit indices or thereversed bit indices with either ‘k’ or ‘n−k’. In some examples, inresponse to the polar coder implementing a shortening scheme, the bankof w comparators may be configured to set bit pattern bits {b₀, b₁, b₂,. . . , b_(w−1)} to the first binary value if the corresponding bitindices or reversed bit indices are less than ‘k’ and other bits to thecomplementary binary value. In some examples, the bank of tv comparatorsmay be configured to set bit pattern bits {b₀, b₁, b₂, . . . , b_(w−1)}to the first binary value if the corresponding bit indices or reversedbit indices are greater than or equal to ‘n−k’ in a puncturing schemeand other bits to the complementary binary value. In this manner, bitpatterns for bit reversed shortening, bit reversed puncturing, naturalshortening and natural puncturing may be generated.

In some examples, frozen bit insertion or frozen bit removal within thepolar coding is performed by the electronic device and comprises atleast two sub-processes and the bit pattern generator is configured toprovide the successive sub-set of (w) bits from the bit pattern vector(b_(k,n)) in each successive t=┌n/w┐ clock cycle that spans a durationof a second sub-process that is preceded by a first sub-process thatspans a series of zero or more clock cycles. In this manner, the firstsub-process can initialise the second sub-process, such that it canselect the K most reliable bits that are not frozen by rate-matching.

In some examples, a first logic circuit is arranged to provide duringthe first sub-process a reliability threshold, k, to an input of the bitpattern generator for use in the second sub-process. In this manner, itcan be guaranteed that there will be K bits that are not frozen by ratematching among the bits selected by the second sub-process havingreliabilities greater than the reliability threshold.

In some examples, the electronic device is configured to support atleast two modes of operation, where a respective mode of operation isemployed in response to whether a number, M, of encoded bits is lessthan a kernal block size, N. In this manner, the bits that are frozen byrate matching can be identified with consideration of the rate matchingmode.

In some examples, the at least two modes of operation comprise at leasttwo from: a repetition mode of operation when M is not less than N, ashortening mode of operation when M<N, a puncturing mode of operationwhen M<N. In this manner, repetition, shortening and puncturing modes ofrate matching can be supported.

In some examples, the first sub-process has zero clock cycles when M isnot less than N, and the second sub-process is performed with thethreshold reliability number, k, set to a number of K bits that adoptthe first binary value in a final output bit sequence. In this manner,support is provided for the repetition mode of operation, which does notfreeze any bits.

In some examples, a controller operably coupled to a second counter isarranged to count a number of clock cycles under control of thecontroller in the first sub-process when M is less than N, and the firstsub-process determines the rank threshold, k, that indicates a number ofbits having a first binary value contained in an intermediate value forthe bit pattern vector (b_(k,n)) output by the bit pattern generatorcircuit. In this manner, it can be guaranteed that there will be K bitsthat are not frozen by rate matching among these bits selected by thesecond sub-process having ranks greater than the rank threshold.

In some examples, a second logic circuit is configured to successivelyperform a binary flag generation process over the series (t=┌n/w┐) ofclock cycles that comprise the second sub-process and configured toprovide a successive sub-set of (w) binary flags in each successivet=┌n/w┐ clock cycle. In this manner, bits that are not frozen by ratematching can be identified.

In some examples, a binary flag is set in the binary flag generationprocess if a corresponding bit in the bit pattern vector (b_(k,n)) isnot frozen by rate matching. In this manner, bits that are not frozen byrate matching can be signaled.

In some examples, a third logic circuit is configured to receive atleast a first input from the second logic circuit and a second inputfrom the bit pattern generator circuit wherein the third logic circuitis configured to provide an output of a first binary value when a bit inthe subset of w bits of the intermediate bit pattern vector (b_(k,n))from the bit pattern generator circuit adopts the first binary value anda corresponding flag from the plurality of binary flags from the secondlogic circuit is set, thereby adjusting a bit pattern vector (b_(k,n))of the intermediate bit pattern based on the at least first and secondinputs. In this manner, bits that are frozen by rate matching can beremoved from the bit pattern.

In some examples, the first logic circuit is arranged to identify thereliability threshold, k, for use in the second sub-process bydetermining whether each uncoded bit is frozen by rate matching and thefirst logic circuit comprises a non-frozen bit counter arranged to counta number of uncoded bits that are not frozen by rate matching in orderof decreasing reliability during the first sub-process, and once thecount reaches the number of final value bits in a final output bitsequence, K, whereupon the rank of the K^(th) most reliable unfrozen bitis determined as the rank threshold, k, and the first logic circuitprovides the rank threshold k as an input to the bit pattern generator.In this manner, the bit pattern generator can identify the set of mostreliable bits, in which there are guaranteed to be K bits that are notfrozen by rate matching.

In some examples, the electronic device further comprises at least oneof: a set of reversed sequence read only memories, ROMs, located in thefirst logic circuit configured to store sets of reversed sequences whereeach successive element of the reversed sequence indicates a position ofeach successive uncoded bit arranged in order of decreasing reliability;a set of deinterleaver ROMs located in the first logic circuitconfigured to store a set of deinterleaver patterns, where each elementof the deinterleaver pattern indicates an interleaved position of apolar encoded bit during rate matching; a set of interleaved sequenceROMs located in the first logic circuit configured to store a set ofinterleaved sequences; a second counter (c1), incremented in successiveclock cycles of the first sub-process, wherein successive addresses of areversed sequence ROM and successive addresses of an interleavedsequence ROM, corresponding to a particular value of N are indexed; arank ROM located in the bit pattern generator configured to storeinformation sufficient to obtain a rank vector (R_(n)) for eachsupported length of the bit pattern, ‘n’; a first set of functionallogic, f1, located in the first logic circuit and configured to obtain aset of binary flags based on received successive sets of elements readfrom the set of reversed sequence ROMs and the set of interleavedsequence ROMs in each successive clock cycle; and an accumulator logiccircuit located in the first logic circuit and configured to receive andcount the set of binary flags up to a number, K, of uncoded bits thatare not frozen by rate matching in a final output bit sequence, and thethreshold reliability number, k, is set to complete the firstsub-process. In this manner, the generation of the bit pattern can becompleted several bits at a time, reducing the number of clock cyclesrequired.

In some examples, the logic circuit is configured to identify a frozenbit as the complementary binary value in the bit pattern vector(b_(k,n)) and identify using the first binary value in the bit patternvector (b_(k,n)) a bit that comprises one from a group of: aninformation bit, a cyclic redundancy check, CRC, bit, a parity-checkfrozen bit, a user equipment identifier, UE-ID, bit, a hash bit. In thismanner, non-frozen bits can be treated separately from frozen-bitsduring the processes of interlacing and deinterlacing.

In some examples, the electronic device may include at least one of: atransmitter comprising an encoder configured to perform the bit patterngeneration process, a receiver comprising a decoder configured toperform the bit pattern generation process.

In a second aspect, examples of the present invention describe anintegrated circuit for an electronic device comprising the bit patterngenerator and the counter according to the first aspect.

In a third aspect, examples of the present invention, a method of methodof polar coding is described. The method includes successivelyperforming a bit pattern generation process over a series (t=┌n/w┐) ofclock cycles by a bit pattern generator; and counting a number ofsuccessive bit pattern generation sub-processes over the series(t=┌n/w┐) of clock cycles. The method further includes providing asuccessive sub-set of (w) bits from a bit pattern vector (b_(k,n)) ineach successive t=┌n/w┐ clock cycle; where the bit pattern vectorcomprises ‘n’ bits, of which ‘k’ bits adopt a first binary value and n−kbits adopt a complementary binary value.

In a fourth aspect, examples of the present invention describe anon-transitory tangible computer program product comprising executablecode stored therein for bit pattern generation according to the thirdaspect.

Although examples of the invention are described with reference to anelectronic device and at least one integrated circuit implementation, itis envisaged that in other examples, the invention may be applied inother implementations and in other applications, such as a wirelesscommunication having a transmitter with a polar encoder and/or areceiver with a polar decoder. For example, the circuits and conceptsherein described may be composed as a hardware implementation within anApplication Specific Integrated Circuit, an Application SpecificInstruction Set Processor, an Application Specific Standard Product, aField Programmable Gate Array, a General Purpose Graphical ProcessingUnit, System on Chip, Configurable Processor, for example. Similarly, itis envisaged that in other examples, a software implementation may becomposed within a Central Processing Unit, a Digital Signal Processor ora microcontroller, for example. Besides wireless communicationtransmitters and receivers, the invention may be composed into awireless communication transceiver, or a communication device for othercommunication channels, such as optical, wired or ultrasonic channels.Furthermore, the invention may be composed into a storage device, inorder to provide FEC for data recovered from optical, magnetic, quantumor solid-state media, for example.

Some examples of the present invention are described with reference tothe New Radio (NR) standard, which is presently being defined by the 3rdGeneration Partnership Project (3GPP) as a candidate for 5th Generation(5G) mobile communication. Presently, polar encoding and decoding hasbeen selected to provide FEC in the uplink and downlink control channelsof the enhanced Mobile BroadBand (eMBB) applications of NR, as well asin the Physical Broadcast Channel (PBCH). Polar encoding and decodinghas also been identified as candidates to provide FEC for the uplink anddownlink data and control channels of the Ultra Reliable Low LatencyCommunication (URLLC) and massive Machine Type Communication (mMTC)applications of NR. Alternatively, some examples of the invention aredescribed without reference to a particular standardised application.More broadly, the invention may be applied in any future communicationstandards that select polar encoding and decoding to provide FEC.Furthermore, the invention may be applied in non-standardisedcommunication applications, which may use polar encoding and decoding toprovide FEC for communication over wireless, wired, optical, ultrasonicor other communication channels. Likewise, the invention may be appliedin storage applications, which use polar encoding and decoding toprovide FEC in optical, magnetic, quantum, solid state and other storagemedia.

In some examples, the circuits and functions herein described may beimplemented using discrete components and circuits, whereas in otherexamples the operations may be performed in a signal processor, forexample in an integrated circuit.

Because the illustrated embodiments of the present invention may, forthe most part, be implemented using electronic components and circuitsknown to those skilled in the art, details will not be explained in anygreater extent than that considered necessary as illustrated below, forthe understanding and appreciation of the underlying concepts of thepresent invention and in order not to obfuscate or distract from theteachings of the present invention.

Detailed Description of Figures

Referring now to FIG. 1, a top-level schematic of a communication unit116 that includes a polar encoder and polar decoder is illustrated,adapted according to examples of the invention. In this example of acommunication unit 116, a skilled artisan will appreciate that a numberof other components and circuits (such as frequency generation circuits,controllers, amplifiers, filters, etc.) are not shown for simplicitypurposes only. In other examples, it is envisaged that the associatedcircuitry in the communication unit 116 may take the form of anintegrated circuit comprising block conditioning in a polar encoder orpolar decoder as well as, for example, for use in a storage unit or anyelectronic device that is designed to use polar encoding or polardecoding. In other examples, it is envisaged that the communication unit116 may take the form of software running on a general purposecomputation processor.

A polar encoder comprises three successive components, namelyinformation block conditioning 101, the polar encoder kernal 102 andencoded block conditioning 103. These components are discussed in thefollowing paragraphs. In order to provide context to the presentdiscussion, FIG. 1 illustrates the communication or storage channel 108,as well as the corresponding components of the polar decoder, namely theinformation block conditioning 112, the polar decoder kernal 111 and theencoded block conditioning 110, although these are operated in thereverse order.

As will be discussed in the following paragraphs, the polar encoderoperates on the basis of an information block 104, kernal informationblock 105, kernal encoded block 106 and encoded block 107.Correspondingly, the polar decoder operates on the basis of a recoveredinformation block 115, recovered kernal information block 114, softkernal encoded block 113 and soft encoded block 109, although these areprocessed in the reverse order.

Therefore, hereinafter throughout the description, claims and drawings,the expression ‘polar coding’ is intended to encompass polar encodingand/or polar decoding, unless specifically referenced otherwise.

In a context of a polar encoder, the input to the information blockconditioning component 101 may be referred to as an information block104, having a block size of K. More specifically, this information blockis a row vector a=[a_(i)]_(i=0) ^(K−1) comprising K information bits,where a_(i)∈{0,1}. The information block conditioning component 101interlaces the K information bits with N-K redundant bits, which may befrozen bits [1], Cyclical Redundancy Check (CRC) bits [2], Parity Check(PC)-frozen bits [3], User Equipment Identification (UE-ID) bits [4], orhash bits [5], for example.

Here, frozen bits may always adopt a logic value of ‘0’, while CRC orPC-frozen bits or hash bits may adopt values that are obtained asfunctions of the information bits, or of redundant bits that havealready been interlaced earlier in the process. The information blockconditioning component 101 generates redundant bits and interlaces theminto positions that are identified by a prescribed method, which is alsoknown to the polar decoder. The information block conditioning component101 may also include an interleaving operation, which may implement abit-reversal permutation [1] for example. The output of the informationblock conditioning component 101 may be referred to as a kernalinformation block 105, having a block size of N. More specifically, thiskernal information block 105 is a row vector u=[u_(j)]_(j=0) ^(N−1)comprising N kernal information bits, where u_(j)∈{0,1}. Here, theinformation block conditioning must be completed such that N is a powerof 2 that is greater than K, in order to provide compatibility with thepolar encoder kernal, which operates on the basis of a generator matrixhaving dimensions that are a power of 2, as will be discussed below. Theinput to the polar encoder kernal 102 is a kernal information block u105 and the output of the polar encoder kernal 102 may be referred to asa kernel encoded block 106, having a block size that matches the kernalblock size N. More specifically, this kernal encoded block 106 is a rowvector: x=[x_(j)]_(j=0) ^(N−1) comprising N kernal encoded bits, wherex_(j)∈{0,1}. Here, the kernal encoded block 106 is obtained according tothe modulo-2 matrix multiplication x=uF^(⊗n), where the modulo-2 sum oftwo bit values may be obtained as their XOR. Here, the generator matrixF^(⊗n) is given by the [n=log 2(N)]th Kronecker power of the kernalmatrix:

$F = {\begin{bmatrix}1 & 0 \\1 & 1\end{bmatrix}.}$

Note that successive Kronecker powers of the kernal matrix may beobtained recursively, where each power F^(⊗n) is obtained by replacingeach logic ‘1’ in the previous power F^(└(n−1)) with the kernal matrixand by replacing each logic ‘0’ with a 2×2 zero matrix. Accordingly, then^(th) Kronecker power F^(⊗n) of the kernal matrix has dimensions of2^(n)×2^(n). For example,

${F^{\otimes 2} = \begin{bmatrix}1 & 0 & 0 & 0 \\1 & 1 & 0 & 0 \\1 & 0 & 1 & 0 \\1 & 1 & 1 & 1\end{bmatrix}},{F^{\otimes 3} = \begin{bmatrix}1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 \\1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 \\1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 \\1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\end{bmatrix}}$

Here, u=[1011] gives x=uF^(⊗2)=[1101] and u=[11001001] givesx=uF^(⊗3)-[00110111].

A skilled artisan will appreciate that the level of integration ofcircuits or components may be, in some instances,implementation-dependent. Furthermore, it is envisaged in some examplesthat a signal processor may be included in a communication unit 116 andbe adapted to implement the encoder and decoder functionality.Alternatively, a single processor may be used to implement a processingof both transmit and receive signals, as shown in FIG. 1, as well assome or all of the baseband/digital signal processing functions.Clearly, the various components, such as the described polar encoder,within a wireless or wired communication unit 116 can be realized indiscrete or integrated component form, with an ultimate structuretherefore being an application-specific or design selection.

In this example, the input to the encoded block conditioning component103 of the polar encoder is a kernal encoded block x 106 and its outputmay be referred to as an encoded block 107, having a block size of M.More specifically, this encoded block is a row vector comprising Mencoded bits b=[b_(k)]_(k=0) ^(M−1), where b_(k,n) ∈{0,1}.

Here, the resultant polar coding rate is given by R=K/M, where theencoded block conditioning 103 must be completed such that ‘M’ isgreater than ‘K’. The encoded block conditioning component 103 may usevarious techniques to generate the ‘M’ encoded bits in the encoded blockb 107, where ‘M’ may be higher or lower than ‘N’. More specifically,repetition [6] may be used to repeat some of the ‘N’ bits in the kernelencoded block ‘x’, while shortening or puncturing techniques [6] may beused to remove some of the ‘N’ bits in the kernel encoded block ‘x’.Note that shortening removes bits that are guaranteed to have logicvalues of ‘0’, while puncturing removes bits that may have either oflogic ‘0’ or ‘1’ values. The encoded block conditioning component mayalso include an interleaving operation. Following polar encoding, theencoded block ‘b’ 107 may be provided to a modulator, which transmits itover a communication channel 108.

Referring now to FIG. 2 and FIG. 3 an example polar encoding process,using an extension of the graphical representation 300 of the generatormatrix F^(⊗3) 203, illustrates the example where a particular frozen bitpattern is used to convert the K=4 information bits a=[1001] 104 intothe M=8 encoded bits b=[00001111] 107. More specifically, informationblock conditioning 101 is used to convert the K=4 information bitsa=[1001]104 into the N=8 kernal information bits u=[00010001] 105. Theseare then converted into the N=8 kernal encoded bits x=[00001111] 106 bythe polar encoder kernal 102 using the polar code graph 203. Here, theinput paths can be traced through the various XOR operations to identifythe output. Finally, encoded block conditioning 103 preserves all kernalencoded bits, to provide the M=8 encoded bits b=[00001111] 107.

In the receiver, the demodulator's role is to recover informationpertaining to the encoded block. However, the demodulator is typicallyunable to obtain absolute confidence about the value of the M bits inthe encoded block 107, owing to the random nature of the noise in thecommunication channel 108. The demodulator may express its confidenceabout the values of the bits in the encoded block 107 by generating asoft encoded block 109, having a block size of M. More specifically,this soft encoded block 109 is a row vector comprising M encoded softbits {tilde over (b)}=[

]_(k=0) ^(M−1). Each soft bit may be represented in the form of aLogarithmic Likelihood Ratio (LLR)

${= {\ln\lbrack \frac{\Pr( {b_{k} = 0} )}{\Pr( {b_{k} = 1} )} \rbrack}},$where Pr(b_(k)=‘0’) and Pr(b_(k)=‘1’) are probabilities that sum to ‘1’.

Here, a positive LLR

indicates that the demodulator has greater confidence that thecorresponding bit b_(k,n) has a value of ‘0’, while a negative LLRindicates greater confidence in the bit value ‘1’. The magnitude of theLLR expresses how much confidence, where an infinite magnitudecorresponds to absolute confidence in this bit value, while a magnitudeof ‘0’ indicates that the demodulator has no information about whetherthe bit value of ‘0’ or ‘1’ is more likely.

In an alternative approach, each soft bit may be represented by a pairof Logarithmic Likelihoods (LLs):{tilde over (b)} _(k)(0)=ln[Pr(b _(k)=0)]{tilde over (b)} _(k)(1)=ln[Pr(b _(k)=1)]A polar decoder comprises three successive components, namely encodedblock conditioning 110, the polar decoder kernal 111 and informationblock conditioning 112, as shown in FIG. 1. These components arediscussed in the following paragraphs.

The input to the encoded block conditioning component 110 of the polardecoder is a soft encoded block {tilde over (b)} 109 and its output maybe referred to as a soft kernal encoded block 113, having a block sizeof N. More specifically, this soft kernal encoded block 113 is a rowvector comprising ‘N’ kernal encoded LLRs {tilde over (x)}=[

]_(j=0) ^(N−1). In order to convert the M encoded LLRs into ‘N’ kernalencoded LLRs, infinite-valued LLRs may be interlaced with the softencoded block 109, to occupy the positions within the soft kernalencoded block that correspond to the ‘0’-valued kernal encoded bits thatwere removed by shortening in the polar encoder. Likewise, ‘0’-valuedLLRs may be interlaced with the soft encoded block 109, to occupy thepositions where kernal encoded bits were removed by puncturing. In thecase of repetition, the LLRs that correspond to replicas of a particularkernal encoded bit may be summed and placed in the correspondingposition within the soft kernal encoded block 109. A correspondingdeinterleaving operation may also be performed, if interleaving wasemployed within the encoded block conditioning component 103 of thepolar encoder.

The input to the polar decoder kernal 111 is a soft kernal encoded block113 and its output may be referred to as a recovered kernal informationblock 114, having a block size of ‘N’. More specifically, this recoveredkernal information block 114 is a row vector comprising ‘N’ recoveredkernal information bits û=

_(j=0) ^(N−1), where û_(j)∈{0,1}. In some examples, he polar decoderkernal 111 may operate using various different algorithms, includingSuccessive Cancellation (SC) decoding [1] and Successive CancellationList (SCL) decoding [7].

The input to the information block conditioning component 112 of thepolar decoder is a recovered kernal information block 114 and its outputmay be referred to as a recovered information block 115, having a blocksize of ‘K’. More specifically, this recovered information block 115 isa row vector â=

_(i=0) ^(K−1) comprising ‘K’ recovered information bits, where

∈{0,1}. The recovered information block may be obtained by removing allredundant bits from the recovered kernal information block û 114. Acorresponding deinterleaving operation may also be performed, ifinterleaving was employed within the information block conditioningcomponent 101 of the polar encoder.

Proposed Block Conditioning Units

As shown in the top-level schematic of FIG. 1, a polar encoder and polardecoder pair includes the four block conditioning modules 101, 103, 110,112.

The information block conditioning module 101 of the polar encoder andthe encoded block conditioning module 110 of the decoder may bothconvert a shorter input into a longer output. More specifically, theinput to the information block conditioning module 101 of the polarencoder comprises K information bits 104. In some examples, the Kinformation bits 104 may be interlaced with N-K redundant bits, in orderto produce N>K kernal information bits 105. Likewise, the input to theencoded block conditioning module 110 of the polar decoder comprises Msoft encoded LLRs 109. In some examples, the M soft encoded LLRs 109 maybe interlaced with N-M punctured or shortened LLRs, in order to produceN>M soft kernal encoded LLRs 113.

In accordance with example embodiments of the invention, an interlacer(for example as illustrated in, and described with reference to FIG. 4and FIG. 5) has been designed to implement these interlacing operationsthat are performed in the information block conditioning module 101 ofthe polar encoder and the encoded block conditioning module 110 of thedecoder.

By contrast, the encoded block conditioning circuit 103 of the polarencoder and the information block conditioning module 112 of the decoderboth convert a longer input into a shorter output. More specifically,the input to the encoded block conditioning circuit 103 of the polarencoder comprises N kernal encoded bits 106. In some examples, N-M ofthese bits may be punctured or shortened, in order to produce M<Nencoded bits 107. Likewise, the input to the information blockconditioning module 112 of the polar decoder comprises N recoveredkernal information bits 114. In some examples, N-K of these bits may beredundant bits and may thus be removed, in order to produce K<Nrecovered information bits 115.

In accordance with examples of the invention the block conditioningcircuits operate on the basis of bit patterns. More specifically, aninformation bit pattern is used in the information block conditioningmodules of the polar encoder and decoder, in order to specify how thecorresponding interlacing and deinterlacing operations may be performed.Likewise, an encoded bit pattern is used in the encoded blockconditioning modules of the polar encoder and decoder, in order tospecify how the corresponding deinterlacing and interlacing operationsmay be performed. In some examples, bit pattern generators 3403 (asillustrated in FIGS. 4, 5, 7, 10, 11, 12 and 13) may be employed by theinterlacer to control the interlacing operations.

Interlacer

Referring now to FIG. 4, an example block diagram of an interlacer 3400is illustrated, according to some example embodiments of the invention.In some examples, the interlacer 3400 may be capable of flexiblyconverting k-element input vectors into corresponding n-element outputvectors, where k and n may vary from use to use. More specifically, theinterlacer 3400 may perform interlacing for each input vector accordingto a bit pattern, which may be selected from a predefined set ofsupported bit patterns, having various combinations of k and n. Theinterlacer 3400 may be used to implement a flexible information blockconditioning circuit, such as information block conditioning circuit 101of FIG. 1, for a polar encoder. In this case, the flexible informationblock conditioning circuit 101 may be capable of converting one k=K-bitinformation block 104 into the corresponding n=N-bit kernal informationblock 105 at a time, where the block sizes A and N may vary fromblock-to-block. Additionally, the interlacer 3400 may be used toimplement a flexible encoded block conditioning circuit 110 for a polardecoder. In this case, the flexible encoded block conditioning circuit110 may be capable of converting one k=M-LLR soft encoded block 109 intothe corresponding n=N-LLR soft kernal encoded block 113 at a time, wherethe block sizes M and N may vary from block-to-block. Note than in boththe polar encoder and polar decoder examples, the kernal block size N isa power of two.

In some examples, the interlacing process is completed over a series oft=┌n/w┐ steps, where w is a power of two that is referred to as thewidth of the proposed interlacer's input port 3401 and output port 3402(with the input port 3401 and output port 3402 of FIG. 4 carryingmultiple signals as illustrated in FIG. 5). This quantifies the numberof elements that the respective ports may consume from the input vectoror generate for the output vector in each step. Here, the output port3402 generates w elements for the output vector in every step, while theinput port 3401 only consumes w elements from the input vector in┌k/w┐<t of the steps, which may be distributed across the t steps, asdetailed below.

The first in each set of w elements of the input and output vectors aremapped to the right-most of the w elements of the input port 3401 andoutput port 3402, with successive elements of the vectors mapped tosuccessive elements of the input port 3401 and output port 3402 fromright to left. Depending on if and how pipelining is applied, each stepof the interlacing process may correspond to one clock cycle in ahardware implementation. Here, each LLR may be represented using thetwo's complement number representation having a same bit-width as theLLR input to a polar decoder kernal, such as the polar decoder kernal111 of FIG. 1. It is noteworthy that the proposed approach processes wpattern bits in each step, which is in contrast to the blockconditioning modules of known designs [14, 15], which are only capableof processing a single pattern bit in each step.

The interlacer 3400 also comprises bit pattern generator 3403, buffer3404, shifter 3405, controller 3406 and insertion 3407 circuits (orlogic or software-based operations). In some examples, each of the wbits 3409 output by the bit pattern generator 3403 in a particular stepof the interlacing process corresponds to the element in thecorresponding position among the w elements generated by the output ofthe proposed interlacer in that step. If the bit has a value ‘1’, thenthe corresponding output element is supplied by the next elementprovided by the input of the interlacer 3400, as will be detailed below.By contrast, if the bit has the value ‘0’, then the corresponding outputelement 3402 is provided by an interlaced element (such as interlacedelement 3501 in FIG. 5). It is noteworthy that, in the case, where: n<w,the bit pattern generator 3403 may append w-n dummy bits to the end ofthe bit pattern, in order to increase its length to w.

In the case of the information block conditioning circuit 101 of thepolar encoder, the interlaced element may be a frozen bit having thevalue ‘0’, a cyclic redundancy check (CRC) bit, a parity check(PC)-frozen bit, a user equipment identifier (UE-ID) bit or a hash bit,for example. In the case of the encoded block conditioning circuit 110of the polar decoder, the interlaced element may be a punctured LLRhaving the value ‘0’, or a shortened LLR having a maximum positive valuesupported by the two's complement fixed-point number representation [6],for example. Note that in some applications, more than one type ofinterlaced element may be required, where the information bits may beinterlaced with both frozen bits and CRC bits, for example. In thiscase, separate bit patterns may be used for each type of interlacedelement. Alternatively, the bit pattern may use ┌log₂(z)┐ bits for eachelement of the bit pattern, where the combination of the log₂(z) bitsmay identify which one of z different types of element is used. Forexample, the bit pairings 10, 01 and 11 may be used to represent the z=3options of frozen bit, CRC bit and information bit, respectively. Inthis case, a decoder circuit may be used to extract the separate bitpatterns for each type of interlaced element.

In each step i∈[0, t−1] of the interlacing process, the controller 3406may count the number P_(i) of 1-valued bits among the w bits 3409provided by the bit pattern generator 3403, as described herein. Thisnumber of elements is compiled for the output of the proposedinterlacing process, by drawing upon two sources of elements: firstly,any elements that reside within the (w−1)-element buffer 3404 andsecondly, the input port 3401 of the interlacer 3400. The controller3406 keeps track of the number R_(i)└[0, w−1] of valid elements that arestored in the buffer 3404 at the beginning of each step of theinterlacing process, where the buffer 3404 is initially empty at thestart of the interlacing process, giving R₀=0. In any steps where thenumber of valid elements in the buffer R_(j) is less than the numberrequired P_(i), the controller 3406 may cause w elements to be drawnfrom the input 3401, on an on-demand basis.

Referring now to FIG. 5, a more detailed example of an interlacer 3500for the case of w=4 is illustrated, according to some exampleembodiments of the invention. As exemplified in FIG. 5, a bit-shiftercircuit 3405 is used to combine elements drawn from the w-element inputport 3401 and the (w−1)-element buffer 3404, producing a (2w−1)-elementoutput containing at least P_(i) valid elements. In cases whereR_(i)<P_(i), the w-element input port 3401 of the proposed interlacer isappended to the left of the elements from the buffer 3404. However, onlyR_(i)∈[0, w−1] of the w−1 elements from the buffer 3404 will be valid,so the controller 3406 directs a bit-shifter circuit 3405 to shift thew-element input port 3401 of the proposed interlacer 3500 byC_(i)=w−1−R_(i) positions to the right, before multiplexing it with theR_(i) elements from the buffer 3404. The bit-shifter circuit 3405 may beimplemented using log₂(w) rows of multiplexers, where each row 3503 usesw−1 multiplexers to implement a different power-of-two shift. As shownin FIG. 5, the control signal for each multiplexer row 3503 may beobtained from the corresponding bit of the binary representation of C₁,where the Most Significant Bit (MSB) drives the row implementing thelargest power-of-two shift and the Least Significant Bit (LSB) drivesthe row implementing the shift of one position. In some examples, it isnoted that the rows may be permuted in any order. A further w−1multiplexers 3502 are required to multiplex the shifted input with thecontents of the buffer 3404, where the right-most R_(i) elements areselected from the buffer 3404 and the remaining elements are selectedfrom the output of the bit-shifter circuit 3405. It is envisaged that inan alternative architecture, the further w−1 multiplexers may bearranged within the same rows of the bit-shifter circuit 3405, reducingthe critical path length of the interlacer 3500. In cases where:R_(i)<P_(i), the above described approach results in valid elements forthe right-most R_(i)+w of the 2w−1 outputs of the bit-shifter circuit3405. By contrast, when R_(i)≥P_(i), no input is taken from the input ofthe interlacer 3500 and the bit-shifter circuit 3405 is disabled. Thisresults in the R_(i) valid elements from the buffer 3404 providing theright-most R_(i) of the 2w−1 outputs of the bit-shifter circuit 3405.

The (2w−1)-element output of the bit-shifter circuit 3405 is provided tothe insertion circuit 3407, which extracts P_(i) elements in positionsdictated by the bit pattern and places all remaining elements into thebuffer 3404, ready for use in the next step of the interlacing process.The insertion circuit 3407 comprises w rows of multiplexers, where thetop-most row comprises 2w−2 multiplexers and each successive row belowit contains one fewer multiplexer than the last. In this manner, eachrow of multiplexers forms a shifting circuit, which is controlled by thevalue of the corresponding bit from the bit pattern. More specifically,if the corresponding bit from the bit pattern is a ‘1’, then the rightmost element at the input to the row is extracted for the output of theinterlacer 3500 and all other elements at the input to the row areshifted to the right by one position, as shown in FIG. 5. The bits ofthe bit pattern are also used to control a set of w multiplexers 3504,which multiplex the elements extracted from the insertion circuit 3407with the corresponding interlaced elements 3501, which may be redundantbits in the case of the information block conditioning module 101 of thepolar encoder or punctured or shortened LLRs in the case of the encodedblock conditioning module 110 of the polar decoder. In cases wheredifferent interlaced elements 3501 have different values, replicas ofthe interlacer 3500 may be operated on the basis of the complementarybit patterns described above. The outputs of these interlacers may thenbe multiplexed together, using the set of w multiplexers 3504 describedabove.

Following a completion of each step of the interlacing process, the(w−1) elements output by the bottom row of the insertion circuit 3407are stored in the buffer 3404. In steps where R_(i)<P_(i), the number ofthese elements that are valid will be given by R_(i+1)=R_(i)+w−P_(i),while R_(i+1)=R_(i)−P_(i) of the elements will be valid in steps whereR_(i)≥P_(i). The buffer 3404 then makes these valid elements availableto the next step of the interlacing process, as described above.

The total number of multiplexers required for the interlacer 3500 isgiven by 3w²/2+wlog₂(w)+w/2−log₂(w)−1. The critical path comprisesw+log₂(w) multiplexers, in the case where all multiplexers of thebit-shifting circuit 3405 are accommodated within the same log₂(w) rows.

FIG. 6 illustrates an example table to operate interlacer 3400 or 3500where w=4, for the case where the k=9 input elements [9, 8, 7, 6, 5, 4,3, 2, 1] are interlaced from right-to-left with ‘0’-valued interlacingelements, according to the n=16-bit pattern [1100011010110101]. In step‘0’, P₀=2 elements are required, but the buffer (for example buffer 3404of FIG. 4 or FIG. 5) contains R₀=0 valid elements, so w=4 elements areconsumed from the input port 3401. Of the w=4 elements, P₀=2 contributeto the output in positions dictated by the bit pattern, with theremaining R₁=2 elements being stored in the buffer 3404. In step ‘1’,P₁=3 elements are required, but the buffer 3404 contains only R₁=2 validelements, so w=4 elements are consumed from the input port 3401. Of theR₁+w=6 elements, P₁=3 contribute to the output in positions dictated bythe bit pattern, with the remaining R₂=3 elements being stored in thebuffer 3404. In step ‘2’, P₂=2 elements are required and the buffer 3404contains R₂=3 valid elements, so no elements are consumed from the inputport 3401. Of the R₂=3 elements, P₂=2 contribute to the output inpositions dictated by the bit pattern, with the remaining R₃=1 elementbeing stored in the buffer 3404. In step ‘3’, P₃=2 elements arerequired, but the buffer 3404 contains only R₃=1 valid element, so theremaining element is consumed from the input 3401, but padded with zerosin order to make up a width of w=4. Both of the R₃+1=2 elementscontribute to the output in positions dictated by the bit pattern.

Bit Pattern Generator

In examples of the invention, a number of alternative designs for thebit pattern generator 3403 are proposed herein, any of which may be usedto generate the information bit pattern used by the interlacer 3400 or3500 in order to implement the information block conditioning circuit101 of the polar encoder. Furthermore, these example designs may be usedto generate the encoded bit pattern used by the interlacers 3400, 3500in order to implement the encoded block conditioning circuit 110 of apolar decoder.

The following sections propose alternative bit pattern generator designsthat may exploit various different combinations of the bit patternproperties.

1) Naive Bit Pattern Generator:

Referring now to FIG. 7, a naive bit pattern generator 4200, for thecase where w=4, is illustrated according to some example embodiments ofthe invention. In a naive implementation, the bit pattern generator 4200may be implemented using a bit pattern Read Only Memory (ROM) 4201,which may store a set of supported bit pattern vectors b_(k,n) eachcorresponding to a particular combination of input and output vectorlengths k and n. In some examples, an off-line pre-computation processmay be used to generate this set of supported bit pattern vectorsb_(k,n) for all supported bit patterns, which may be read from the bitpattern ROM 4201 as required during the on-line block conditioningprocess.

Referring now to FIG. 8, an example table of contents 3700 of the bitpattern ROM, when using the Polarization Weight (PW) bit patternconstruction of [8] for all combinations of n′ {2, 4, 8, 16} and k′ {1,2, 3, . . . , n−1}, is illustrated according to some example embodimentsof the invention. In the example table of FIG. 8, a set of informationbit pattern vectors b_(k,n) is generated for all combinations of n {2,4, 8, 16} and k′ {1, 2, 3, . . . , n−1}. Here, a ‘1’-valued element inthe information bit pattern vector b_(k,n) indicates that thecorresponding bit in the kernal information block, say kernalinformation block 105 of FIG. 1, should be an information bit.Meanwhile, a ‘0’-valued element in the information bit pattern vectorb_(k,n) corresponds to a redundant bit, which may be a frozen bit, CRCbit, PC-frozen bit, UE-ID bit, or hash bit, for example. Note that inalternative arrangements, a ‘1’-valued element in the information bitpattern vector b_(k,n) indicates that the corresponding bit in thekernal information block should be a non-frozen bit, which may be aninformation bit, CRC bit, PC-frozen bit or UE-ID bit or hash bit, forexample. Meanwhile, a ‘0’-valued element in the information bit patternvector b_(k,n) may correspond to a frozen bit. Alternatively, separatebit pattern vectors may be used to indicate whether each bit belongs toeach type of bit.

Referring back to FIG. 7, in order to support all combinations of n∈{2,4, 8, . . . , n_(max)} and k∈{1, 2, 3, . . . , n−1}, the total capacityrequirement of the bit pattern ROM 4201 is given by Σ_(n∈){2, 4, 8, . .. , n_(max})(n²−n), which corresponds to 1.33 Mbit in the case wheren_(max)=1024. The bit pattern ROM 4201 has a width of w bits and eachbit pattern vector b_(k,n) is stored across ┌n/w┐ consecutive addresses,where n is the output vector length supported by the bit pattern vectorb_(k,n). In some examples, in cases where: n<w, the bit pattern vectorb_(k,n) may be appended with w-n dummy bits, such that it occupies thewidth of a single address in the bit pattern ROM 4201. As shown in FIG.7, k and n may be used to index a look-up table 4202, in order toidentify the start address of each particular bit pattern vectorb_(k,n). During each of the t=┌n/w┐ successive steps of the blockconditioning process, a counter 4203 c may be incremented from 0 to t−1and used as an offset from the start address of the bit pattern ROM4201, in order to read successive w-element sub-sets {b₀, b₁, b₂, . . ., b_(w−1)} 4204 of the bit pattern vector b_(k,n). In examples of theinvention, the counter 4203 c is configured to count a number of clockcycles up to ┌n/w┐.

2) Bit Pattern Generator that Exploits a Nested Property:

The amount of ROM required for the generation of bit pattern vectorsb_(k,n) may be significantly reduced in cases where the bit patternvectors b_(k,n) obey the nested property. Here, the nested property issatisfied if the ‘1’-valued bits in a bit pattern vector b_(k,n) for aparticular combination of k and n always form a sub-set of the‘1’-valued bits in a bit pattern vector b_(k,n) for any combination of agreater k and the same n. For example, the nested property is satisfiedby the information bit pattern vectors b_(k,n) that are generated by thePW technique, as well as by the FRActally eNhanced Kernel (FRANK)technique of [9]. Rather than storing a bit pattern vector b_(k,n) foreach supported combination of k and n, a rank ROM 3801 according toexample embodiments of the invention may be used to store a rank vectorR_(n) for each supported n. The rank vector R_(n) for a particular valueof n comprises the integers in the range 0 to n−1, permuted in an orderthat corresponds to the rank of each bit position, where a particularrank indicates the maximum k for which the corresponding bit in the bitpattern vector b_(k,n) has the value 0.

Referring now to FIG. 9 an example table of the contents of a Rank ROM(such as rank ROM 3801 of FIG. 10), for a set of rank vectors R_(n)generated using a PW bit pattern construction of [8] for all n {2, 4, 8,16, 32}, is illustrated according to some example embodiments of theinvention. Here, lower ranks correspond to more reliable bits within thekernal information block, such as kernal information block 105 of FIG.1.

Referring now to FIG. 10, a bit pattern generator exploiting the nestedproperty, for the case where w=4, is illustrated according to someexample embodiments of the invention. Here, the bit pattern vectorb_(k,n) may be generated for a particular combination of k and n byusing a bank of w comparators 3802, in order to compare each element ofthe rank vector R_(n) with k. If a rank is less than k, then thecorresponding bit pattern vector b_(k,n) bit is set to ‘1’, otherwisethe corresponding bit pattern bit is set to 0′. Here, the bit patternbit may be obtained by representing the rank and k using the two'scomplement fixed-point number representation, performing a subtraction,and then retaining the MSB of the result.

In some examples, and assuming that all entries in the rank ROM 3801 arestored using fixed point numbers having a width of log₂(n_(max)) bits,the total capacity required for the rank ROM 3801 to store all rankvectors R_(n) for n∈{2, 4, 8, . . . , n_(max)} may be given by(2n_(max)−2)log₂(n_(max)) bits. In this way, the rank ROM storesinformation sufficient to obtain a rank vector R_(n) for each supportedlength of the bit pattern ‘n’. This corresponds to 19.98 kbit in a casewhere n_(max)=1024, representing a 98.5% reduction compared to the totalcapacity required for the bit pattern ROM in the aforementioned naivebit pattern generator.

Alternatively, the total capacity required can be reduced toΣ_(n∈{2, 4, 8, . . . , n) _(max) _(}) n log₂(n) bits, if differentwidths of log₂(n) bits are used to store the fixed-point numbers fordifferent values of n, corresponding to 18.00 kbit for n_(max)=1024.

In some examples, the rank ROM 3801 has a width of wlog₂(n_(max)) bitsor w log₂(n) bits, depending on whether the fixed-point numberrepresentation for each rank comprises log₂ (n_(max)) bits or log₂ (n)bits. Here, each rank vector R_(n) is stored across ┌n/w┐ consecutiveaddresses, where n is the output vector length supported by the rankvector R_(n). It is noteworthy that in cases where n<w, the rank vectormay be appended with w-n dummy elements, such that it occupies the widthof a single address in the rank ROM 3801.

In some examples, n may be used to index a look-up table 3803, in orderto identify the start address of each particular rank vector R_(n).Alternatively, a separate multiplexed rank ROM 3801 may be used to storethe rank vector R_(n) corresponding to each supported value of n, inwhich case each may employ a start address of ‘0’.

During each of the t=┌n/w┐ successive steps of the block conditioningprocess, a counter 4203 c may be incremented from ‘0’ to ‘t−1’ and usedas an offset from the start address of the rank ROM 3801, in order toread successive w-element sub-sets of the rank vector R_(n). Thesesub-sets of the rank vector R_(n) may then be converted into w patternbits {b₀, b₁, b₂, . . . , b_(w−1)} 4204 using the bank of w comparators3802, as described above.

In some examples, it is envisaged that a counter 4203 c configured tocount from 0 to t−1 may be used for this example circuit and approach,as well as the example circuit of the previous approach.

It is noteworthy that the rank vector R_(n) described above is differentto the index vector Q_(n) described in [8, 9]. More specifically, therank vector R_(n) ranks the reliabilities of the bits within the kernalinformation block 105, where the rank of the first bit in the kernalinformation block 105 appears at one of the vector and the rank of thelast bit appears at the other end of the vector. By contrast, the indexvector Q_(n) provides the indices of the bits within the kernalinformation block 105 sorted in order of reliability, where the index ofthe most reliable bit appears at one end of the vector and the index ofthe least reliable bit appears at the other end of the vector. However,an approach based on storing the index vector Q_(n) may require the useof an interleaver or other complex circuitry to interpret the indexvector Q_(n) and produce the bit pattern vector b_(k,n). By contrast,the proposed approach relies only on simple comparators 3802 tointerpret the rank vector R_(n) and produce the bit pattern vectorb_(k,n), as described above.

It is envisaged in alternative examples that the elements of the rankvectors R_(n) described above may be subtracted from n−1 and storedinstead in this adjusted form. In this way, the rank ROM storesinformation sufficient to obtain a rank vector R_(n) for each supportedlength of the bit pattern ‘n’. In the examples of the information bitpattern vectors b_(k,n) generated using the PW and FRANK techniques,this adjustment would cause bits within the kernal information block 105having higher reliabilities to correspond to adjusted ranks havinghigher values, rather than lower values as in the non-adjusted approach.Note that this adjustment is equivalent to reversing the order of thenon-adjusted ranks shown in FIG. 9, owing to the symmetric property ofthe PW technique. In the descriptions above, each comparison todetermine if a non-adjusted rank is less than k may be replaced by acomparison to determine if an adjusted rank is greater than or equal ton−k.

3) Bit Pattern Generator Exploiting Nested and Symmetric Properties:

In this bit pattern generator example, the total capacity required forthe rank ROM 3801 described above may be reduced by 50% in cases wherethe bit pattern vectors b_(k,n) obey the nested property and thesymmetric property. Here, the symmetric property is satisfied if anypair of elements in the rank vector R_(n) having the indices i and n−i−1sum to n−1, for all n and for all i∈[0, n−1]. For example, the symmetricproperty is satisfied by the information bit pattern vectors b_(k,n)that are generated by the PW technique, but not those generated by theFRANK technique of [9] in general.

In some examples, when the symmetric property is satisfied, the rank ROM3801 may only need to store the first half of each rank vector R_(n). Inthe case where fixed point numbers having a constant width of log₂(n_(max)) bits are used, this reduces the total capacity required forthe rank ROM 3801 to store all rank vectors R_(n) for n∈{2, 4, 8, . . ., n_(max)} to (n_(max)−1) log₂(n_(max)) bits, which corresponds to 9.99kbit in the case where n_(max)=1024. In this way, the rank ROM storesinformation sufficient to obtain a rank vector R_(n) for each supportedlength of the bit pattern ‘n’.

Alternatively, this reduces the total capacity required toΣ_(n∈{2, 4, 8, . . . , n) _(max) _(}) n log₂ (n)/2 bits, in the casewhere fixed point numbers having varying widths of log₂(n) bits areused. The rank ROM 3801 has a width of w ranks and each rank vectorR_(n) is stored across ┌n/(2w)┐ consecutive addresses, where n is theoutput vector length supported by the rank vector R_(n).

It is noteworthy that in cases where n/2<w, the rank vector R_(n) may beappended with w-n dummy elements and stored across the width of a singleaddress in the rank ROM 3801.

Referring now to FIG. 11, a bit pattern generator 4000 exploiting thenested and symmetric properties, for the case where w=4, is illustratedaccording to some example embodiments of the invention. Here, n may beused to index a look-up table 3803, in order to identify the startaddress of each particular rank vector R_(n). Alternatively, a separatemultiplexed rank ROM 3801 may be used to store the rank vector R_(n)corresponding to each supported value of n, in which case each mayemploy a start address of ‘0’.

In some examples, the bit pattern generator 4000 may be used tointerface with the reduced-capacity rank ROM 3801 and generate the bitpattern vectors b_(k,n). During each of the t=┌n/w┐ successive steps ofthe block conditioning process, a counter 4203 c may be incremented from‘0’ to ‘t−1’ and used to generate an offset from the start address ofthe rank ROM 3801. During the first half of the t=┌n/w┐ successive stepsof the block conditioning process when c<┌n/(2w)┐, successive w-elementsub-sets of the rank vector R_(n) are read from incremental addresses inthe rank ROM 3801, where the offset from the start address is given byc.

Referring back to the example of FIG. 10, the bank of w comparators 3802may be used to convert these sub-sets of the rank vector R_(n) into wpattern bits{b₀, b₁, b₂, . . . , b_(w−1)} 4204. In this example, duringthe second half of the process when c≥┌n/(2w)┐, w-element sub-sets ofthe rank vector R_(n) are read from decremental addresses in the rankROM 3801, the offset from the start address may be given by (┌n/w┐−c−1).In this way, the same addresses are read as during the first half of theblock conditioning process, but in reverse order. In this example, amultiplexer 4004 may be used to provide (┌n/w┐−c−1) rather than c as theoffset from the start address of the rank ROM 3801. During this secondhalf of the process, if a rank is greater than or equal to n−k, then thecorresponding bit pattern bit is set to ‘1’, otherwise it is set to ‘0’.This may be implemented by using a multiplexer 4001 in order to providen−k as the input to the bank of w comparators 3802, rather than k, aswell as by using a bank of w NOT gates 4002 to invert the output of thecomparators 3802. Furthermore, a bank of w multiplexers 4003 may be usedto reverse the order of the w pattern bits {b₀, b₁, b₂, . . . , b_(w−1)}4204 during the second half of the process, as shown in FIG. 11.

It is envisaged that in alternative examples, the elements of the rankvectors R_(n) described above may be subtracted from n−1 and stored inthis adjusted form instead. In this way, the rank ROM stores informationsufficient to obtain a rank vector R_(n) for each supported length ofthe bit pattern ‘n’. Here, each comparison to determine if anon-adjusted rank is less than k may be replaced by a comparison todetermine if an adjusted rank is greater than or equal to n−k. Likewise,each comparison to determine if a non-adjusted rank is greater than orequal to n−k may be replaced by a comparison to determine if an adjustedrank is less than k.

4) Bit Pattern Generator Exploiting the Nested, Recursive and ArithmeticProperties:

In some examples, in cases where the bit pattern vectors b_(k,n) obeynested, recursive and arithmetic properties, the amount of ROM requiredfor the generation of bit pattern vectors b_(k,n) can be significantlyfurther reduced. Here, the recursive property is satisfied if the indexvectors Q_(n) associated with successive values of n∈{2, 4, 8, . . . ,n_(max)} can be generated by performing simple operations upon thepreceding index vector Q_(n/2). For example, in the PW sequence of [8],the index vector Q_(n) can be obtained by interlacing Q_(n/2) withQ_(n/2)+n/2, according to a particular interlacing pattern P_(n). Thearithmetic property is satisfied if a bit reliability metric can beobtained for each of the n bits in the output vector based only on itsindex in the range ‘0’ to ‘n−1’. In the PW sequence of [8], thereliability of each kernal information bit may be determined bycalculating a β expansion upon the binary representation of each bitindex in the range ‘0’ to ‘n−1’. The elements in a corresponding vectorof these bit reliabilities β_(n) may be sorted in order to obtain theindex vector Q_(n), or may be ranked in order to obtain the rank vectorRdn.

Referring now to FIG. 12, a bit pattern generator 4400 exploiting thenested, recursive and arithmetic properties, for the case where w=4, isillustrated according to some example embodiments of the invention. Insome examples, in cases where the bit pattern vectors b_(k,n) obeynested, recursive and arithmetic properties, the example bit patterngenerator 4400 may obtain the bit pattern vector b_(k,n) for aparticular combination of k and n. Here, a recursive circuit 4401 may beused to convert the value of n−k into the index Q_(n)(n−k) of the bithaving the (n−k)^(th) highest bit reliability. This recursive circuit4401 may exploit the recursive property to obtain Q_(n)(n−k) based on arecursive combination of elements from the preceding index vectors{Q_(n/2)(k), Q_(n/4)(k), Q_(n/8)(k), . . . }. In some examples, it isnoteworthy that rather than unpacking the entirety of each successiveindex vector, the unpacking may target only the particular elements thatare required to obtain Q_(n)(n−k). In the case of the PW sequence, themodule may include a circuit for performing interlacing, as well as aROM for storing some or all of the interlacing patterns{P₁, P₂, P₄, . .. , P_(n) _(max) }.

In some examples, it is also noteworthy that by also exploiting thesymmetric property, this ROM may have a total capacity requirement of 1kbit. To provide a reference for this significant improvement, let usconsider the explanation in [8], whereby a vector P_(n) is defined,together with a technique for generating Q_(n) based on {P₂, P₄, . . .P_(n)}. Here, P_(n) is a binary vector that satisfies the symmetricproperty. Since n can vary between {2, 4, 8, . . . 1024} at run time,the capability to generate {Q₂, Q₄, Q₈, . . . , Q₁₀₂₄} is required. As aresult, the capability to generate all of {P₂, P₄, P₈, . . . P₁₂₄} isneeded. In accordance with example embodiments of the present invention,and by exploiting the symmetric property of P_(n), the P_(n) vectors canbe generated by storing only the first half of each of {P₂, P₄, P₈, . .. P₁₀₂₄}. Here, n/2 bits are required to store the first half of P_(n),giving a total of 1023 bits for all of {P₂, P₄, P₈, . . . P₁₀₂₄}. Inthis way, the recursive circuit may be considered to unpack compressedinformation, in order to obtain Q_(n)(n−k).

Following this, an arithmetic circuit 4402 may use the arithmeticproperty to convert the index Q_(n)(n−k) of the bit having the(n−k)^(th) rank into a bit reliability metric (β(Q_(n)(n−k)). This valuemay then be stored in a register 4403 and used throughout the process ofgenerating the bit pattern vector b_(k,n).

More specifically, during each of the t=┌n/w┐ successive steps of theblock conditioning process, a counter c 4203 may be incremented from ‘0’to ‘t−1’ and used to obtain bit indices {cw, cw+1, cw+2, . . . , cw+w−1}for successive w-element sub-sets of the bit pattern vector b_(k,n). Insome examples, this may be achieved using the arrangement of amultiplier 4404 and a bank of w−1 adders 4405, as shown in FIG. 12.Following this, a bank of w replicas 4406 of the arithmetic circuit maybe used to compute corresponding bit reliabilities {β[cw], β[cw+1],β[cw+2], . . . , β[cw+w−1]}, which may then be compared withβ(Q_(n)(n−k)) using a bank of w comparators 4407, in order to obtain thecorresponding w elements of the bit pattern vector b_(k,n). In the PWsequence, greater β expansion values imply greater bit reliabilities andso the bank of w comparators 4407 obtains the bit pattern bits {b₀, b₁,b₂, . . . , b_(w−1)} 4204 by determining whether the corresponding bitreliabilities {β[cw], β[cw+1], β[cw+2], . . . , β[cw+w−1]} are greaterthan or equal to β(Q_(n)(n−k)).

It is noteworthy that it may be possible to achieve a power saving byexploiting the recursive property of the bit pattern vector b_(k,n). Forexample, in the case of a PW sequence the recursive properties may beused to determine relationships between bits in the kernal informationblock. More specifically, it may be determined that if a particular bitis chosen as a frozen bit, then this guarantees that particular otherbits will also be chosen as frozen bits. Likewise, it may be determinedthat if a particular bit is chosen as an information bit, then thisguarantees that particular other bits will also be chosen as informationbits. This may be exploited in the bit pattern generator 4400 of FIG.12, to disable particular arithmetic circuits during particular steps inthe process, whenever the corresponding bit pattern bit can bedetermined based on decisions that have been made in earlier steps ofthe process.

In some examples, it is envisaged that the approach of FIG. 12 may besimplified further in the case of encoded block conditioning, where thebit reliabilities are simple functions of the bit indices. Here, duringeach of the t=┌n/w┐ successive steps of the encoded block conditioningprocess, a counter c 4203 may be incremented from ‘0’ to ‘t−1’ and usedto control a circuit that provides successive w-element sub-sets of thebit pattern vector b_(k,n), depending on the values of n and k.

Referring now to FIG. 13 circuits for generating w bits from aparticular bit pattern in each step of the encoded block conditioningprocess are illustrated, according to examples of the invention. Forexample the illustrated circuits include: (a) Block puncturing; (b)Block shortening; (c) Bit reversal puncturing; and (d) Bit reversalshortening, according to some example embodiments of the invention.Suitable circuits for block puncturing, block shortening, bit reversalpuncturing and bit reversal shortening [16] are illustrated in FIGS.13a-13d . Here, a multiplier 4101 and a bank of w−1 adders 4102 are usedto convert the counter c 4203 into the indices of the bits in thecurrent sub-set of the bit pattern vector {cw, cw+1, cw+2, . . . ,cw+w−1}. In the bit-reversal schemes of FIGS. 13c and 13d , a bank of wreverse modules 4103 is used to reverse the order of the bits in thelog₂ (n)-bit binary representation of each bit index, in order toproduce the reversed bit indices {cw, cw+1, cw+2, . . . , cw+w−1}.Finally, a bank of w comparators is used to compare either the bitindices or the reversed bit indices with either k or n−k. Morespecifically, the bit pattern bits {b₀, b₁, b₂, . . . , b_(w−1)} are setto one if the corresponding bit indices or reversed bit indices are lessthan k in the shortening schemes of FIGS. 13b and 13d . By contrast, thebit pattern bits {b₀, b₁, b₂, . . . , b_(w−1)} are set to one if thecorresponding bit indices or reversed bit indices are greater than orequal to n−k in the puncturing schemes of FIGS. 13a and 13c . Comparedto FIG. 12, it may be observed that the arithmetic module 4401 and therecursive module 4402 cancel each other out in all cases shown in FIGS.13a-13d . In the case of FIGS. 13c and 13d , the functionality of thearithmetic modules 4406 is performed by the bit reversal operations4103.

Examples of Proposed Hardware Implementations for Frozen Bit Insertionand Removal

Several polar code sequences were proposed and compared in [17] and theHuawei sequence was selected for the 3GPP New Radio polar code at 3GPPTSG RAN WG1 Meeting #90 [18, Al 6.1.4.2.2]. The Huawei sequence from[17] is defined for a maximum mother code block length of N_(max)=1024bits and the sequence Q_(N) for a shorter power-of-two mother blocklength N can be extracted by exploiting the sequence's nested property.For example, the sequence for N=64 is Q_(f)4=[0, 1, 2, 4, 8, 16, 32, 3,5, 9, 6, 17, 10, 18, 12, 33, 20, 34, 24, 36, 7, 11, 40, 19, 13, 48, 14,21, 35, 26, 37, 25, 22, 38, 41, 28, 42, 49, 44, 50, 15, 52, 23, 56, 27,39, 29, 43, 30, 45, 51, 46, 53, 54, 57, 58, 60, 31, 47, 55, 59, 61, 62,63]. Here, each successive element Q_(N)[u] (where u∈[0, N−1]) of thesequence Q_(N) indicates the position (in the range [0, N−1]) of thenext more reliable uncoded bit of the polar code, where Q_(N) [0] andQ_(N)I[N−1] give the positions of the least and most reliable bits,respectively. For example, Q₆₄[5]=16 indicates that the bit in position16 is more reliable than the bits in positions Q₆₄[0] to Q₆₄[4], butless reliable than the bits in positions Q₆₄[6] to Q₆₄[63].

Two polar code rate matching schemes were proposed and compared in [19]and Option 2 was selected at 3GPP TSG RAN WG1 Meeting #90 [18, Al6.1.4.2.3]. Option 2 from [19] defines a sub-block interleaver, whichdecomposes the polar encoded bits into 32 equal-length sub-blocks, whichare reordered according to the interleaver pattern n=[0, 1, 2, 4, 3, 5,6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24,25, 26, 28, 27, 29, 30, 31]. Here, each element π[m] (where m∈[0,31]) ofthe interleaver pattern T indicates the position (in the range [0,31])that the interleaved sub-block in position m is sourced from. Forexample, π[9]=16 indicates that the interleaved sub-block in position 9is sourced from the sub-block that was in position 16 beforeinterleaving. Furthermore, dependent on the uncoded block length K andthe encoded block length M, Option 2 from [19] defines rules whichgovern the selection of the mother code block length N and the selectionof puncturing, shortening or repetition. Crucially, Option 2 from [19]also defines rules which govern the selection of frozen bits, whichdepends on all of the other aspects of this rate matching scheme.

More specifically, the rate matching scheme influences which of the Nuncoded bits are provided by the K information and Cyclical RedundancyCheck (CRC) bits. The remaining N−K uncoded bits are provided by frozenbits, which may be scrambled by User Equipment Identification (UE-ID)bits. In the absence of rate matching, the positions of the Kinformation and CRC bits would be selected by using the sequence Q_(N)to identify the K uncoded bits having the highest reliability, with allother uncoded bits becoming frozen. However, when rate matching isemployed, this requires a set of frozen bits to be identifiedindependently of and before applying the sequence. Following this, the Kinformation and CRC bits are positioned within the remaining uncodedbits by using the sequence Q_(N) to identify those having the highestreliability, with all other remaining uncoded bits becoming frozen.

This section proposes examples of hardware implementations that canperform the frozen bit insertion and removal processes for several bitsat a time, allowing them to be completed using a small number of clockcycles. More specifically, this allows frozen bits to be interlaced withinformation bits and CRC bits, before polar encoding. Likewise, thisallows the frozen bits to be deinterlaced from the information and CRCbits, following polar decoding. Examples of the proposed approach mayalso be adapted to interlace and deinterlace Parity Check (PC) bits.Examples of the proposed hardware implementations do not requirecircuits for sorting, interleaving or performing other complexoperations, nor do they require an excessive amount of ROM for storingpre-computed frozen bit positions or intermediate variables. Someenvisaged examples of the proposed hardware implementations are detailedbelow.

During a first sub-process 4701, as identified in FIGS. 16, 21, and 25,some examples of the proposed hardware implementations consider w_(Q)uncoded bit positions at a time in order of decreasing reliability,considering whether each successive uncoded bit is frozen by ratematching. This continues until K number of bits that are not frozen byrate matching have been found, whereupon the reliability of theK^(th)-most reliable unfrozen bit is determined and referred to as thethreshold reliability 3804. During a second sub-process 4702, asidentified in FIGS. 16, 21-24 and 26, w_(R) uncoded bit positions areconsidered at a time in their natural order. Each of the w_(R) uncodedbit positions is determined to be an information or CRC bit if itsreliability is no less than the threshold reliability 3804 and if it isnot frozen by rate matching, otherwise it is determined to be a frozenbit. In this way, a bit pattern is generated w_(R) bits at a time 3409throughout the second sub-process 4702, which identifies whether eachuncoded bit is an information or CRC bit, or if it is a frozen bit. Atthe same time, the bit pattern may be used to interlace 101 ordeinterlace 112 w_(R) uncoded bits at a time in their natural order.More specifically, the information and CRC bits may be interlaced withthe frozen bits throughout the second sub-process 4702, in order toimplement frozen bit insertion 101 during polar encoding. Likewise, theinformation and CRC bits may be deinterlaced from the frozen bitsthroughout the second sub-process 4702, in order to implement frozen bitremoval 112 during polar decoding.

Some examples of the proposed hardware implementations for frozen bitinsertion and removal are detailed in the schematic of FIG. 16, wherethe top and bottom halves correspond to the first and secondsub-processes 4701 and 4702, respectively. This schematic includes foursets of ROMs 4202, 3801, 4203, 4204, as detailed below. The operation ofthese ROMs and the logic shown in FIG. 16 is coordinated by thecontroller 4201, as detailed below.

-   -   1) ROMs

As shown in FIG. 16, some examples of the proposed hardwareimplementations employ four sets of ROMs, as follows.

-   -   A set of reversed sequence ROMs 4202 stores the set of reversed        sequences {Q₃₂ ^(←), Q₆₄ ⁷⁷, Q₁₂₈ ^(←), . . . , Q₁₀₂₄ ^(←)}.        Here, each successive element Q_(N) ^(←)[u]=Q_(N)[N−u−1] (where        u∈[0, N−1]) of the reversed sequence Q_(N) ^(←) indicates the        position (in the range [0,N−1]) of the next less reliable        uncoded bit of the polar code, where Q_(N) ^(←)[0] and Q_(N)        ^(←)[N−1] give the positions of the most and least reliable        bits, respectively.    -   A set of rank ROMs 3801 stores a set of rank sequences {R₃₂,        R₆₄, R₁₂₈, . . . , R₁₀₂₄}. Here, each element R_(N)[u] (where        u∈[0, N−1]) of the rank sequence R_(N) indicates the reliability        ranking (in the range [0,N−1]) of the corresponding uncoded bit        of the polar code, where a lower value R_(N)[u] indicates a        higher reliability. For example, R_(N)[u₁]=0 and R_(N)[u₂]=N−1        indicate that the uncoded bits u₁ and u₂ are the most and least        reliable bits, respectively. The relationship between the        reversed sequence Q_(N) ^(←) and the rank sequence R_(N) is such        that Q_(N) ^(←)[R_(N)[u]]=u.    -   A set of deinterleaver ROMs 4203 stores a set of deinterleaver        patterns {π₃₂ ⁻¹, π₆₄ ⁻¹, π₁₂₈ ⁻¹, . . . , π₁₀₂₄ ⁻¹}. Here, each        element π_(N) ⁻¹[u] (where u∈[0,N−1]) of the deinterleaver        pattern π_(N) ⁻¹ indicates the position (in the range [0,N−1])        that the polar encoded bit in position u is interleaved to,        during rate matching. The relationship between the deinterleaver        pattern π_(N) ⁻¹ and the interleaver pattern π is such that        π[┌π_(N) ⁻¹[u]·32/N┐]=┌u·32/N┐. Furthermore, all elements π_(N)        ⁻¹[u] in π_(N) ⁻¹ that evaluate to the same value of ┌π_(N)        ⁻¹[u]·32/N┐ appear in consecutive positions within πN⁻¹, in        ascending order.    -   A set of interleaved sequence ROMs 4204 stores a set of        interleaved sequences {Q₃₂ ^(π), Q₆₄ ^(π), Q₁₂₈ ^(π), . . . ,        Q₁₀₂₄ ^(π)}. Here, each element Q_(N) ^(π)[u] of the interleaved        sequence Q_(N) ^(π) is obtained as Q_(N) ^(π)[u]=π_(N) ⁻¹[Q_(N)        ^(←)[u]].

Each address in each reversed sequence ROM 4202 and each interleavedsequence ROM 4204 stores w_(Q) elements of the respective sequences,where w_(Q) is a power of two. More specifically, each successive groupof w_(Q) consecutive elements of each reversed sequence Q_(N) ^(←) arestored in successive addresses of the corresponding reversed sequenceROM 4202, as exemplified for N=64 and w_(Q)=8 in FIG. 17. Likewise, eachsuccessive group of w_(Q) consecutive elements of each interleavedsequence Q_(N) ^(π) are stored in successive addresses of thecorresponding interleaved sequence ROM 4204, as exemplified for N=64 andw_(Q)=8 in FIG. 18. More specifically, each element in these ROMs 4202,4204 is obtained according to Q_(N) ^(←)[c,i]=Q_(N) ^(ƒ)[c·w_(Q)+i] andQ_(N) ^(π)[c,i]=Q_(N) ^(π)[c·w_(Q)+i], where c∈[0, N/w_(Q)−1] is thecorresponding address and i∈[0, w_(Q)−1] is the index of the elementwithin that address.

By contrast, each address in each deinterleaver ROM 4203 and each rankROM 3801 stores w_(R) elements of the respective sequences, where w_(R)is a power of two that may be selected independently of w_(Q). Morespecifically, each successive group of w_(R) consecutive elements ofeach deinterleaver pattern π_(N) ⁻¹ are stored in successive addressesof the corresponding deinterleaver ROM 4203, as exemplified for N=64 andw_(R)=4 in FIG. 19. Likewise, each successive group of w_(R) consecutiveelements of each rank sequence R_(N) are stored in successive addressesof the corresponding rank ROM 3801, as exemplified for N=64 and w_(R)=4in FIG. 20. More specifically, each element in these ROMs 4203, 3801 isobtained according to π_(N) ⁻¹ [c, i]=π_(N) ⁻¹[c·w_(R)+1] andR_(N)[c,i]=R_(N)[c·w_(R)+i], where c∈[0, N/w_(R)−1] is the correspondingaddress and i∈[0, w_(R)−1] is the index of the element within thataddress.

Note that in cases where N<w_(Q) or N<w_(R), each sequence stored in acorresponding ROM 4202, 3801, 4203, 4204 may be appended with w_(Q)−N orw_(R)−N dummy elements having the value N−1, in order to fill a singleaddress of the ROM. Note that rather than storing sequences of the sametype in separate ROMs corresponding to each supported value of N, thesesequences could be stored within different address spaces of a singlelarger ROM. In this case, the value of N may be used to index a lookuptable 3803, which identifies the start address of the correspondingsequence.

Assuming that all entries in the ROMs 4202, 3801, 4203, 4204 are storedusing fixed point numbers having a width of log₂(N_(max))=10 bits, thetotal capacity required for the ROMs to store all sequences Q_(N) ^(←),Q_(N) ^(π), π_(N) ⁻¹ and R_(N) for N∈{32, 64, 128, . . . , 1024} is78.75 kbit. Alternatively, the total capacity required can be reduced to71.62 kbit, if different widths of log₂(N) bits are used to store thefixed-point numbers for different values of N.

2) Logic and Controller

As shown in FIG. 16, some examples of the proposed hardwareimplementations for frozen bit insertion and removal comprise four setsof ROMs 4202, 3801, 4203, 4204 and various logic circuits. These operateunder the coordination of the controller 4201 shown in FIG. 16,according to the flowchart of FIG. 21. As described above, some examplesof the proposed hardware implementations complete the processes offrozen bit insertion or removal using two sub-processes 4701 and 4702,which correspond to the left and right halves of FIG. 21.

At the beginning of the first sub-process 4701, the N logic 4205 of FIG.16 is used to compute the mother code block size N, as a function of thenumber K of information and CRC bits, as well as of the number M ofpolar encoded bits that remain after rate matching. As shown in FIG. 21,if M<N is not satisfied 4703, then the first sub-process 4701 can beimmediately concluded by setting the rank threshold k equal to K 4704,where k implements the reliability threshold 3804 mentioned above.Otherwise, the first sub-process 4701 must use further computations inorder to determine the rank threshold k 3804.

In this case, the controller 4201 resets the counters c₁ and c₂ shown inFIG. 16 to zero 4705. In successiven clock cycles, successive addressesof the reversed sequence ROM 4202 and the interleaved sequence ROM 4204corresponding to the particular value of N are indexed using the counterc₁ 4206, which is incremented in each clock cycle 4706. As shown inFIGS. 16 and 21, the w_(Q) consecutive elements Q_(N) ^(←)[c₁,0] toQ_(N) ^(←)[c₁, w_(Q)−1] and Q_(N) ^(π)[c₁, 0] to Q_(N) ^(π)[c₁, w_(q)−1]of the reversed sequence Q_(N) ^(←) and the interleaved sequence Q_(N)^(π) are read 4707, 4708 from the reversed sequence ROM 4202 and theinterleaved sequence ROM 4204, respectively.

Each successive set of elements read from the reversed sequence andinterleaved sequence ROMs 4202, 4204 in each successive clock cycle isprovided to the first set of f logic 4207 shown in FIG. 16. As shown inFIG. 21, this f logic 4207 obtains a set of w_(Q) binary flags bycomputing b₁[i]=f(K, M, N, Q_(N) ^(←)[c₁,i], Q_(N) ^(π)[c₁, i]) for eachvalue of i∈[0, w_(Q)−1] in parallel 4709, where

$\begin{matrix}{{{f( {K,M,N,u,{\pi_{N}^{- 1}\lbrack u\rbrack}} )} = \mspace{101mu}{M \geq {N\mspace{14mu}{OR}\mspace{14mu}( {{K/M} > {{7/16}\mspace{11mu}{AND}\mspace{14mu}{\pi_{N}^{- 1}\lbrack u\rbrack}} < M} )\mspace{20mu}{OR}}}}\mspace{20mu}( {{K/M}\; \leq {{7/16}\mspace{14mu}{AND}\mspace{14mu}{\pi_{N}^{- 1}\lbrack u\rbrack}} \geq {N - {M\mspace{14mu}{AND}\mspace{14mu}( {( {M \geq {3{N/4}\mspace{14mu}{AND}\mspace{25mu} u} \geq \lceil {{3{N/4}} - {M/2}} \rceil} )\mspace{14mu}{OR}\mspace{14mu}( {M < {3{N/4}\mspace{14mu}{AND}\mspace{14mu} u} \geq \lceil {{9{N/16}} - {M/4}} \rceil} )} )}}} )} & (1)\end{matrix}$

The binary flags b₁[0] to b₁[w_(Q)−1] obtained in each clock cycle areprovided to the accumulator logic 4208 shown in FIG. 16. As shown inFIG. 21, this uses an index i which is initially set to 0 (4710) and isincremented (4711) towards w_(Q)−1 (4712), in order to consider thebinary flags in order from b₁[0] to b₁[w_(Q)−1]. At the same time, thecounter c₂ 4209 is incremented once (4713) for each of the binary flagshaving the value 1 (4714). When the counter c₂ reaches the value K(4715), the threshold rank k 3804 is set equal to c₁w_(Q)+i+1 (4716),whereupon the first sub-process 4701 is completed. More specifically,the first sub-process 4701 continues through successive clock cyclesuntil c₂ K is satisfied (4717), which will typically occur before c₁reaches the index of the final address of the reversed sequence andinterleaved sequence ROMs 4202, 4204.

As shown in FIG. 16 and FIG. 21, the threshold rank k 3804 is stored ina register 4210, so that it can be used throughout the secondsub-process 4702. At the start of the second sub-process 4702, thecontroller 4201 resets the counter c₃ 4203 shown in FIG. 16 to zero4718. In successive clock cycles, successive addresses of thedeinterleaver ROM 4203 and the rank ROM 3801 corresponding to theparticular value of N are indexed using the counter c₃, which isincremented in each clock cycle 4721, until c₃≥N/w_(R)−1 is satisfied4729. As shown in FIG. 16 and FIG. 21, the w_(R) consecutive elementsπ_(N) ⁻¹[c₃,0] to π_(N) ⁻¹[c₃, w_(R)−1] and R_(N)[c₃, 0] to R_(N)[c₃,w_(R)−1] of the deinterleaver pattern π_(N) ⁻¹ and the rank sequenceR_(N) are read 4719, 4720 from the deinterleaver ROM 4203 and the rankROM 3801, respectively.

Each successive set of elements read from the deinterleaver ROM 4203 ineach successive clock cycle is provided to the second set of f logic4211 shown in FIG. 16. Note that since the first and second sets of flogic are not used simultaneously, they may share the same hardware bymultiplexing between the inputs provided in the first sub-process 4701and those provided in the second sub-process 4702. As shown in FIG. 21,this f logic obtains a set of w_(R) binary flags by computing b₂[i]=f(K, M, N, c₃w_(R)+i, π_(N) ⁻¹[c₃, i]) of (1) 4722 for each value ofi∈[0, w_(R)−1] 4726, 4727, 4728 in parallel. At the same time, eachsuccessive set of elements read from the rank ROM 3801 in eachsuccessive clock cycle is provided to the set of w_(R) comparators 3802shown in FIG. 16. As shown in FIG. 21, these comparators obtain a set ofw_(R) binary flags 4204 by computing b₃ [i]=R_(N)[c₃, i]<k for eachvalue of i∈[0, w_(R)−1] in parallel 4723. Then, the binary flags b₂[0]to b₂[w_(R)−1] and b₃[0] to b₃[w_(R)−1] are provided to a set of w_(R)AND gates 4212, which obtain a set of w_(R) binary flags 3409 bycomputing b₄[i]=(b₂[i] AND b₃[i]) for each value of i∈[0, w_(R)−1] inparallel 4724, as shown in FIG. 21. Tables 22 to 24 illustrate the bitpatterns b₄[0] to b₄[w_(R)−1] 3409 that are generated in each clockcycle of the second sub-process 4702, for examples in which repetition,shortening and puncturing are used.

In each successive clock cycle of the second sub-process 4702, the bitpattern b₄[0] to b₄[w_(R)−1] may be used to interlace 101 or deinterlace112 each successive set of w_(R) uncoded bits in parallel 4725, as shownin FIG. 16 and FIG. 21. Each of the bits in the bit pattern b₄[0] tob₄[w_(R)−1] having the value ‘1’ indicates that the correspondinguncoded bit is provided by an information or CRC bit. Likewise, each ofthe bit pattern bits having the value 0 indicates that the correspondinguncoded bit is a frozen bit, which may be scrambled by the UE-ID. Duringpolar encoding, the interlacer of FIG. 16 operates on the basis ofFirst-In First-Out (FIFO) buffering. In each clock cycle, an input FIFObuffer supplies a number of information and CRC bits equal to the numberof 1s in the corresponding bit pattern. Meanwhile, a second input FIFObuffer supplies a number of UE-ID scrambled frozen bits equal to thenumber of 0s in the bit pattern. Alternatively, if UE-ID scrambling isnot used and all frozen bits adopt a value of ‘0’, then the second FIFObuffer can be replaced with a circuit that supplies the correspondingnumber of 0-valued bits. The interlacer 101 of FIG. 16 may theninterlace the information, CRC and frozen bits according to thecorresponding bit pattern, producing w_(R) number of uncoded bits inparallel, in each clock cycle of the second sub-process 4702. Likewise,during polar decoding, the deinterlacer 112 of FIG. 16 may perform thereverse operation for w_(R) number of uncoded bits in each clock cycle,where the information and CRC bits are provided to an output FIFObuffer.

The total number of clock cycles required to complete the frozen bitinsertion and removal processes is given by the sum of the number usedin each of the first and second sub-processes 4701 and 4702. FIG. 25characterises the number of clock cycles required to complete the firstsub-process 4701 as a function of K and M, for the worst case wherew_(Q)=1. When w_(Q) adopts the value of a higher power of two, thenumber of clock cycles required may be obtained by linearly scaling downthose of FIG. 25 and taking the ceiling. It may be observed that greaternumbers of clock cycles are required at coding rates of K/M>7/16, whereshortening is employed. This is because shortening uses some of the mostreliable uncoded bit positions for frozen bits. A smaller number ofclock cycles is required when employing puncturing, since this typicallyuses the least reliable bit positions for frozen bits. Morespecifically, the number of clock cycles used in the first sub-process4701 with w_(Q)=1 is equal to k 3804 in the case of shortening orpuncturing. By contrast, no clock cycles are required when employingrepetition, as described above. Note however that the first sub-process4701 may be completed in parallel with CRC generation and interleavingduring polar encoding and in parallel with channel interleaving duringpolar decoding. Owing to this, the first sub-process 4701 does notnecessarily impose additional latency. The number of clock cyclesrequired to complete the second sub-process 4702 is given by ┌N/w_(R)┐,as characterised in FIG. 26, for the worst case where w_(R)=1. Whenw_(R) adopts the value of a higher power of two, the number of clockcycles required may be obtained by linearly scaling down those of FIG.26 and taking the ceiling. The second sub-process 4702 can streamuncoded bits into a polar encoder kernal or stream uncoded bits out of apolar decoder kernal alongside their operation, without imposingadditional latency.

This section has proposed some examples of hardware implementations thatcan perform the frozen bit insertion and removal processes for severalbits at a time, allowing them to be completed using a small number ofclock cycles. More specifically, this allows frozen bits (which may bescrambled using UE-ID bits) to be interlaced with information bits andCRC bits, before polar encoding. Likewise, this allow the frozen bits tobe deinterlaced from the information and CRC bits, following polardecoding. Some examples of the proposed hardware implementations do notrequire circuits for sorting, interleaving or performing other complexoperations, nor do they require an excessive amount of ROM for storingpre-computed frozen bit positions or intermediate variables. Some, andin some instances all, operations of the proposed hardwareimplementations can be performed alongside other polar encoding ordecoding operations and so they do not impose any additional latency.

Referring now to FIG. 14, a high-level flowchart 1400 of a polar coderoperation performed by a bit pattern generator is illustrated inaccordance with some example embodiments of the invention. The flowchartcomprises, at 1402, successively performing a bit pattern generationprocess over a series (t=┌n/w┐) of clock cycles by a bit patterngenerator (3403). At 1404, the flowchart moves to counting a number ofsuccessive bit pattern generation sub-processes over the series(t=┌n/w┐) of clock cycles. At 1406, a successive sub-set of (w) bitsfrom a bit pattern vector (b_(k,n)) in each successive t=┌n/w┐ clockcycle is provided; where the bit pattern vector comprises ‘n’ bits, ofwhich ‘k’ bits adopt a first binary value and n−k bits adopt acomplementary binary value.

Referring now to FIG. 15, there is illustrated a typical computingsystem 1500 that may be employed to implement polar encoding accordingto some example embodiments of the invention. Computing systems of thistype may be used in wireless communication units. Those skilled in therelevant art will also recognize how to implement the invention usingother computer systems or architectures. Computing system 1500 mayrepresent, for example, a desktop, laptop or notebook computer,hand-held computing device (PDA, cell phone, palmtop, etc.), mainframe,server, client, or any other type of special or general purposecomputing device as may be desirable or appropriate for a givenapplication or environment. Computing system 1500 can include one ormore processors, such as a processor 1504. Processor 1504 can beimplemented using a general or special-purpose processing engine suchas, for example, a microprocessor, microcontroller or other controllogic. In this example, processor 1504 is connected to a bus 1502 orother communications medium. In some examples, computing system 1500 maybe a non-transitory tangible computer program product comprisingexecutable code stored therein for implementing polar encoding.

Computing system 1500 can also include a main memory 1508, such asrandom access memory (RAM) or other dynamic memory, for storinginformation and instructions to be executed by processor 1504. Mainmemory 1508 also may be used for storing temporary variables or otherintermediate information during execution of instructions to be executedby processor 1504. Computing system 1500 may likewise include a readonly memory (ROM) or other static storage device coupled to bus 1502 forstoring static information and instructions for processor 1504.

The computing system 1500 may also include information storage system1510, which may include, for example, a media drive 1512 and a removablestorage interface 1520. The media drive 1512 may include a drive orother mechanism to support fixed or removable storage media, such as ahard disk drive, a floppy disk drive, a magnetic tape drive, an opticaldisk drive, a compact disc (CD) or digital video drive (DVD) read orwrite drive (R or RW), or other removable or fixed media drive. Storagemedia 1518 may include, for example, a hard disk, floppy disk, magnetictape, optical disk, CD or DVD, or other fixed or removable medium thatis read by and written to by media drive 1512. As these examplesillustrate, the storage media 1518 may include a computer-readablestorage medium having particular computer software or data storedtherein.

In alternative embodiments, information storage system 1510 may includeother similar components for allowing computer programs or otherinstructions or data to be loaded into computing system 1500. Suchcomponents may include, for example, a removable storage unit 1522 andan interface 1520, such as a program cartridge and cartridge interface,a removable memory (for example, a flash memory or other removablememory module) and memory slot, and other removable storage units 1522and interfaces 1520 that allow software and data to be transferred fromthe removable storage unit 1518 to computing system 1500.

Computing system 1500 can also include a communications interface 1524.Communications interface 1524 can be used to allow software and data tobe transferred between computing system 1500 and external devices.Examples of communications interface 1524 can include a modem, a networkinterface (such as an Ethernet or other NIC card), a communications port(such as for example, a universal serial bus (USB) port), a PCMCIA slotand card, etc. Software and data transferred via communicationsinterface 1524 are in the form of signals which can be electronic,electromagnetic, and optical or other signals capable of being receivedby communications interface 1524. These signals are provided tocommunications interface 1524 via a channel 1528. This channel 1528 maycarry signals and may be implemented using a wireless medium, wire orcable, fibre optics, or other communications medium. Some examples of achannel include a phone line, a cellular phone link, an RF link, anetwork interface, a local or wide area network, and othercommunications channels.

In this document, the terms ‘computer program product’,‘computer-readable medium’ and the like may be used generally to referto media such as, for example, memory 1508, storage device 1518, orstorage unit 1522. These and other forms of computer-readable media maystore one or more instructions for use by processor 1504, to cause theprocessor to perform specified operations. Such instructions, generallyreferred to as ‘computer program code’ (which may be grouped in the formof computer programs or other groupings), when executed, enable thecomputing system 1500 to perform functions of embodiments of the presentinvention. Note that the code may directly cause the processor toperform specified operations, be compiled to do so, and/or be combinedwith other software, hardware, and/or firmware elements (e.g., librariesfor performing standard functions) to do so.

In an embodiment where the elements are implemented using software, thesoftware may be stored in a computer-readable medium and loaded intocomputing system 1500 using, for example, removable storage drive 1522,drive 1512 or communications interface 1524. The control logic (in thisexample, software instructions or computer program code), when executedby the processor 1504, causes the processor 1504 to perform thefunctions of the invention as described herein.

In the foregoing specification, the invention has been described withreference to specific examples of embodiments of the invention. It will,however, be evident that various modifications and changes may be madetherein without departing from the scope of the invention as set forthin the appended claims and that the claims are not limited to thespecific examples described above.

The connections as discussed herein may be any type of connectionsuitable to transfer signals from or to the respective nodes, units ordevices, for example via intermediate devices. Accordingly, unlessimplied or stated otherwise, the connections may for example be directconnections or indirect connections. The connections may be illustratedor described in reference to being a single connection, a plurality ofconnections, unidirectional connections, or bidirectional connections.However, different embodiments may vary the implementation of theconnections. For example, separate unidirectional connections may beused rather than bidirectional connections and vice versa. Also,plurality of connections may be replaced with a single connection thattransfers multiple signals serially or in a time multiplexed manner.Likewise, single connections carrying multiple signals may be separatedout into various different connections carrying subsets of thesesignals. Therefore, many options exist for transferring signals.

Those skilled in the art will recognize that the architectures depictedherein are merely exemplary, and that in fact many other architecturescan be implemented which achieve the same functionality.

Any arrangement of components to achieve the same functionality iseffectively ‘associated’ such that the desired functionality isachieved. Hence, any two components herein combined to achieve aparticular functionality can be seen as ‘associated with’ each othersuch that the desired functionality is achieved, irrespective ofarchitectures or intermediary components. Likewise, any two componentsso associated can also be viewed as being ‘operably connected,’ or‘operably coupled,’ to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundariesbetween the above described operations merely illustrative. The multipleoperations may be combined into a single operation, a single operationmay be distributed in additional operations and operations may beexecuted at least partially overlapping in time. Moreover, alternativeembodiments may include multiple instances of a particular operation,and the order of operations may be altered in various other embodiments.

The present invention is herein described with reference to anintegrated circuit device comprising, say, a microprocessor configuredto perform the functionality of a polar decoder. However, it will beappreciated that the present invention is not limited to such integratedcircuit devices, and may equally be applied to integrated circuitdevices comprising any alternative type of operational functionality.Examples of such integrated circuit device comprising alternative typesof operational functionality may include, by way of example only,application-specific integrated circuit (ASIC) devices,field-programmable gate array (FPGA) devices, or integrated with othercomponents, etc. Furthermore, because the illustrated embodiments of thepresent invention may for the most part, be implemented using electroniccomponents and circuits known to those skilled in the art, details havenot been explained in any greater extent than that considered necessary,for the understanding and appreciation of the underlying concepts of thepresent invention and in order not to obfuscate or distract from theteachings of the present invention. Alternatively, the circuit and/orcomponent examples may be implemented as any number of separateintegrated circuits or separate devices interconnected with each otherin a suitable manner.

Also for example, the examples, or portions thereof, may implemented assoft or code representations of physical circuitry or of logicalrepresentations convertible into physical circuitry, such as in ahardware description language of any appropriate type.

Also, the invention is not limited to physical devices or unitsimplemented in non-programmable hardware but can also be applied inprogrammable devices or units able to perform the desired polar encodingby operating in accordance with suitable program code, such asminicomputers, personal computers, notepads, personal digitalassistants, electronic games, automotive and other embedded systems,cell phones and various other wireless devices, commonly denoted in thisapplication as ‘computer systems’.

However, other modifications, variations and alternatives are alsopossible. The specifications and drawings are, accordingly, to beregarded in an illustrative rather than in a restrictive sense.

In the claims, any reference signs placed between parentheses shall notbe construed as limiting the claim. The word ‘comprising’ does notexclude the presence of other elements or steps then those listed in aclaim. Furthermore, the terms ‘a’ or ‘an,’ as used herein, are definedas one or more than one. Also, the use of introductory phrases such as‘at least one’ and ‘one or more’ in the claims should not be construedto imply that the introduction of another claim element by theindefinite articles ‘a’ or ‘an’ limits any particular claim containingsuch introduced claim element to inventions containing only one suchelement, even when the same claim includes the introductory phrases ‘oneor more’ or ‘at least one’ and indefinite articles such as ‘a’ or ‘an.’The same holds true for the use of definite articles. Unless statedotherwise, terms such as ‘first’ and ‘second’ are used to arbitrarilydistinguish between the elements such terms describe. Thus, these termsare not necessarily intended to indicate temporal or otherprioritization of such elements. The mere fact that certain measures arerecited in mutually different claims does not indicate that acombination of these measures cannot be used to advantage.

REFERENCES

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The invention claimed is:
 1. An electronic device configured to performpolar coding, the electronic device comprising: a bit pattern generatorconfigured to successively perform a bit pattern generation process overa series, t=┌n/w┐, of clock cycles; and a counter, c, operably coupledto the bit pattern generator and configured to count a number ofsuccessive bit pattern generation sub-processes over the series,t=┌n/w┐, of clock cycles, wherein the bit pattern generator isconfigured to: provide a successive sub-set of, w, bits from a bitpattern vector, b_(k,n), in each successive t=┌n/w┐ clock cycle; wherethe bit pattern vector comprises n bits, of which ‘k’ bits adopt a firstbinary value and n−k bits adopt a complementary binary value, andwherein the bit pattern generator comprises a bank of (w) comparators,and wherein the successive sub-set of, w, bits cause each of w bitpattern bits {b₀, b₁, b₂, . . . , b_(w−1)} to be obtained from acorresponding comparator in the bank of w comparators.
 2. The electronicdevice of claim 1, wherein the bit pattern generator comprises a rankread only memory, ROM, configured to store information sufficient toobtain a rank vector, R_(n), for each supported length of the bitpattern, ‘n’, wherein the rank vector, R_(n), for a length of the bitpattern, ‘n’, comprises integers in a range of ‘0’ to ‘n−1’, permuted inan order that corresponds to a rank of each bit position, and whereinthe bit pattern vector, b_(k,n), is generated for a respectivecombination of the number, k, of bits in a bit pattern adopting thefirst binary value and the length of the bit pattern ‘n’ using the bankof w comparators that compares each element of the rank vector, R_(n)with ‘k’.
 3. The electronic device of claim 2, wherein the rank of eachbit position indicates a maximum value for the number ‘k’ out of ‘n’bits in the bit pattern adopting the first binary value, for which acorresponding bit in the bit pattern vector, b^(k,n), has acomplementary binary value, and wherein each comparison determineswhether the element of the rank vector, R_(n), is less than ‘k’.
 4. Theelectronic device of claim 2, wherein at least one of the following isadopted: a length of the bit pattern n is used to index a second look-uptable, in order to identify a start address of each particular rankvector, R_(n); the rank ROM comprises multiple multiplexed rank ROMs,wherein one multiplexed rank ROM is configured to store the rank vector,R_(n), corresponding to each supported value of the length of the bitpattern ‘n’.
 5. The electronic device of claim 2, wherein at least oneof the following is adopted: all entries in the rank ROM are storedusing fixed point numbers having a width of log₂(n_(max)) bits, wheren_(max) is a maximum of the supported bit pattern lengths; all entriesin the rank ROM for values of n are stored using fixed point numbershaving a width of log₂(n) bits.
 6. The electronic device of claim 2,wherein each address of the rank ROM is configured to store wfixed-point numbers and wherein the rank ROM, in cases where n<w, isconfigured to append the rank vector, R_(n), with w-n dummy elements,such that the rank vector, R_(n), occupies a width of a single addressin the rank ROM.
 7. The electronic device of claim 2, wherein the rankROM is operably coupled to the counter, c, such that during eachsuccessive sub-process of the bit pattern generation process, thecounter, c, is configured to increment a counter value from ‘0’ to ‘t−1’wherein the counter value is used as an offset from a start address ofthe rank ROM in order to read successive w-element sub-sets of the rankvector, R_(n).
 8. The electronic device of claim 2, wherein a bitpattern bit of the bit pattern vector b_(k,n) is obtained byrepresenting both a rank value and k using a two's complementfixed-point number representation, and the bit pattern generator circuitperforms a two's complement subtraction of ‘k’ from the rank value andthen uses a most significant bit, MSB, as a value of the bit patternbit.
 9. The electronic device of claim 1, wherein frozen bit insertionor frozen bit removal within the polar coding is performed by theelectronic device and the frozen bit insertion or frozen bit removalcomprises at least two sub-processes and the bit pattern generator isconfigured to provide the successive sub-set of (w) bits from the bitpattern vector (b_(k,n)) in each successive t=┌n/w┐ clock cycle thatspans a duration of a second sub-process that is preceded by a firstsub-process that spans a series of zero or more clock cycles and whereina first logic circuit is arranged to provide during the firstsub-process a reliability threshold, k, to an input of the bit patterngenerator for use in the second sub-process.
 10. The electronic deviceof claim 9, wherein the electronic device is configured to support atleast two modes of operation, where a respective mode of operation isemployed in response to whether a number, M, of encoded bits is lessthan a kernal block size, N and wherein the at least two modes ofoperation comprise at least two from: a repetition mode of operationwhen M is not less than N, a shortening mode of operation when M<N, apuncturing mode of operation when M<N.
 11. The electronic device ofclaim 10, wherein the first sub-process has zero clock cycles, and thesecond sub-process is performed when M is not less than N, and thethreshold reliability number, k, is set to a number of K bits that adoptthe first binary value in a final output bit sequence.
 12. Theelectronic device of claim 10, further comprising a controller operablycoupled to a second counter arranged to count a number of clock cyclesunder control of the controller in the first sub-process when M is lessthan N, and the first sub-process determines the rank threshold, k, thatindicates a number of bits having the first binary value contained in anintermediate value for the bit pattern vector, b_(k,n), output by thebit pattern generator.
 13. The electronic device of claim 12, furthercomprising a second logic circuit configured to successively perform abinary flag generation process over the series (t=┌n/w┐) of clock cyclesthat comprise the second sub-process and configured to provide asuccessive sub-set of w binary flags in each successive t=┌n/w┐ clockcycle and wherein a binary flag is set in the binary flag generationprocess if a corresponding bit in the bit pattern vector, b_(k,n) is notfrozen by rate matching.
 14. The electronic device of claim 13, furthercomprising a third logic circuit configured to receive at least a firstinput from the second logic circuit and a second input from the bitpattern generator wherein the third logic circuit is configured toprovide an output of a first binary value when a bit in the subset of wbits of the intermediate bit pattern vector, b_(k,n), from the bitpattern generator adopts the first binary value and a corresponding flagfrom a plurality of binary flags from the second logic circuit is set,thereby adjusting a bit pattern vector, b_(k,n), of the intermediate bitpattern based on the at least first and second inputs.
 15. Theelectronic device of claim 9, wherein the first logic circuit isarranged to identify the reliability threshold, k, for use in the secondsub-process by determining whether each uncoded bit is frozen by ratematching and the first logic circuit comprises a non-frozen bit counterarranged to count a number of uncoded bits that are not frozen by ratematching in order of decreasing reliability during the firstsub-process, and once the count reaches the number of final value bitsin a final output bit sequence, K, whereupon the rank of the K^(th) mostreliable unfrozen bit is determined as the rank threshold, k, and thefirst logic circuit provides the rank threshold k as an input to the bitpattern generator.
 16. The electronic device of claim 9, wherein theelectronic device further comprises at least one of: a set of reversedsequence read only memories, ROMs, located in the first logic circuitconfigured to store sets of reversed sequences where each successiveelement of the reversed sequence indicates a position of each successiveuncoded bit arranged in order of decreasing reliability; a set ofdeinterleaver ROMs located in the first logic circuit configured tostore a set of deinterleaver patterns, where each element of thedeinterleaver pattern indicates an interleaved position of a polarencoded bit during rate matching; a set of interleaved sequence ROMslocated in the first logic circuit configured to store a set ofinterleaved sequences; a second counter, c1, incremented in successiveclock cycles of the first sub-process, wherein successive addresses of areversed sequence ROM and successive addresses of an interleavedsequence ROM, corresponding to a particular value of N are indexed; arank ROM located in the bit pattern generator configured to storeinformation sufficient to obtain a rank vector, R_(n), for eachsupported length of the bit pattern, ‘n’; a first set of functionallogic, f1, located in the first logic circuit and configured to obtain aset of binary flags based on received successive sets of elements readfrom the set of reversed sequence ROMs and the set of interleavedsequence ROMs in each successive clock cycle; and an accumulator logiccircuit located in the first logic circuit and configured to receive andcount the set of binary flags up to a number, K, of uncoded bits thatare not frozen by rate matching in a final output bit sequence, and thethreshold reliability number, k, is set to complete the firstsub-process.
 17. The electronic device of claim 9, wherein the firstlogic circuit is configured to identify a frozen bit as thecomplementary binary value in the bit pattern vector, b_(k,n), andidentify using the first binary value in the bit pattern vector,b_(k,n), a bit that comprises one from a group of an information bit, acyclic redundancy check, CRC, bit, a parity-check frozen bit, a userequipment identifier, UE-ID, bit, a hash bit.
 18. The electronic deviceof claim 1, wherein the electronic device comprises at least one of: atransmitter comprising an encoder configured to perform the bit patterngeneration process, a receiver comprising a decoder configured toperform the bit pattern generation process.
 19. An integrated circuitfor an electronic device configured to perform polar coding, theintegrated circuit comprising: a bit pattern generator configured tosuccessively perform a bit pattern generation process over a series(t=┌n/w┐) of clock cycles; and a counter, c, operably coupled to the bitpattern generator and configured to count a number of successive bitpattern generation sub-processes over the series, t=┌n/w┐, of clockcycles, wherein the bit pattern generator is configured to: provide asuccessive sub-set of (w) bits from a bit pattern vector (b_(k,n)) ineach successive t=┌n/w┐ clock cycle; where the bit pattern vectorcomprises n bits, of which ‘k’ bits adopt a first binary value and n−kbits adopt a complementary binary value and wherein the bit patterngenerator comprises a bank of (w) comparators, and wherein thesuccessive sub-set of w bits cause each of w bit pattern bits {b₀, b₁,b₂, . . . , b_(w−1)} to be obtained from a corresponding comparator inthe bank of w comparators.
 20. A method of polar coding, wherein themethod comprises: successively performing a bit pattern generationprocess over a series, t=┌n/w┐, of clock cycles by a bit patterngenerator; and counting a number of successive bit pattern generationsub-processes over the series t=┌n/w┐ of clock cycles, providing asuccessive sub-set of w bits from a bit pattern vector, b_(k,n), in eachsuccessive t=┌n/w┐ clock cycle; where the bit pattern vector comprises‘n’ bits, of which ‘k’ bits adopt a first binary value and n−k bitsadopt a complementary binary value and wherein the bit pattern generatorcomprises a bank of w comparators, and wherein the successive sub-set of(w) bits cause each of w bit pattern bits {b₀, b₁, b₂, . . . , b_(w−1)}to be obtained from a corresponding comparator in the bank of wcomparators.